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clk: mediatek: reset: Support nonsequence base offsets of reset registers

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The bank offsets are not serial for all reset registers.
For example, there are five infra reset banks for MT8192: 0x120, 0x130,
0x140, 0x150 and 0x730.

To support this,
- Change reg_ofs to rst_bank_ofs which is a pointer to base offsets of
  the reset register.
- Add a new define RST_NR_PER_BANK to define reset number for each
  reset bank.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Link: https://lore.kernel.org/r/20220523093346.28493-8-rex-bc.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Rex-BC Chen 2022-05-23 17:33:34 +08:00 committed by Stephen Boyd
parent 2d2a290058
commit 723e367114
15 changed files with 85 additions and 43 deletions
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6
drivers/clk/mediatek/clk-mt2701-eth.c
View File

@ -36,10 +36,12 @@ static const struct mtk_gate eth_clks[] = {
GATE_ETH(CLK_ETHSYS_CRYPTO, "crypto_clk", "ethif_sel", 29),
};
static u16 rst_ofs[] = { 0x34, };
static const struct mtk_clk_rst_desc clk_rst_desc = {
.version = MTK_RST_SIMPLE,
.rst_bank_nr = 1,
.reg_ofs = 0x34,
.rst_bank_ofs = rst_ofs,
.rst_bank_nr = ARRAY_SIZE(rst_ofs),
};
static const struct of_device_id of_match_clk_mt2701_eth[] = {

6
drivers/clk/mediatek/clk-mt2701-g3d.c
View File

@ -35,10 +35,12 @@ static const struct mtk_gate g3d_clks[] = {
GATE_G3D(CLK_G3DSYS_CORE, "g3d_core", "mfg_sel", 0),
};
static u16 rst_ofs[] = { 0xc, };
static const struct mtk_clk_rst_desc clk_rst_desc = {
.version = MTK_RST_SIMPLE,
.rst_bank_nr = 1,
.reg_ofs = 0xc,
.rst_bank_ofs = rst_ofs,
.rst_bank_nr = ARRAY_SIZE(rst_ofs),
};
static int clk_mt2701_g3dsys_init(struct platform_device *pdev)

6
drivers/clk/mediatek/clk-mt2701-hif.c
View File

@ -33,10 +33,12 @@ static const struct mtk_gate hif_clks[] = {
GATE_HIF(CLK_HIFSYS_PCIE2, "pcie2_clk", "ethpll_500m_ck", 26),
};
static u16 rst_ofs[] = { 0x34, };
static const struct mtk_clk_rst_desc clk_rst_desc = {
.version = MTK_RST_SIMPLE,
.rst_bank_nr = 1,
.reg_ofs = 0x34,
.rst_bank_ofs = rst_ofs,
.rst_bank_nr = ARRAY_SIZE(rst_ofs),
};
static const struct of_device_id of_match_clk_mt2701_hif[] = {

11
drivers/clk/mediatek/clk-mt2701.c
View File

@ -735,18 +735,21 @@ static const struct mtk_fixed_factor infra_fixed_divs[] = {
FACTOR(CLK_INFRA_CLK_13M, "clk13m", "clk26m", 1, 2),
};
static u16 infrasys_rst_ofs[] = { 0x30, 0x34, };
static u16 pericfg_rst_ofs[] = { 0x0, 0x4, };
static const struct mtk_clk_rst_desc clk_rst_desc[] = {
/* infrasys */
{
.version = MTK_RST_SIMPLE,
.rst_bank_nr = 2,
.reg_ofs = 0x30,
.rst_bank_ofs = infrasys_rst_ofs,
.rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs),
},
/* pericfg */
{
.version = MTK_RST_SIMPLE,
.rst_bank_nr = 2,
.reg_ofs = 0x0,
.rst_bank_ofs = pericfg_rst_ofs,
.rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs),
},
};

11
drivers/clk/mediatek/clk-mt2712.c
View File

@ -1258,18 +1258,21 @@ static const struct mtk_pll_data plls[] = {
0, 31, 0x0300, 4, 0, 0, 0, 0x0304, 0),
};
static u16 infrasys_rst_ofs[] = { 0x30, 0x34, };
static u16 pericfg_rst_ofs[] = { 0x0, 0x4, };
static const struct mtk_clk_rst_desc clk_rst_desc[] = {
/* infra */
{
.version = MTK_RST_SIMPLE,
.rst_bank_nr = 2,
.reg_ofs = 0x30,
.rst_bank_ofs = infrasys_rst_ofs,
.rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs),
},
/* peri */
{
.version = MTK_RST_SIMPLE,
.rst_bank_nr = 2,
.reg_ofs = 0x0,
.rst_bank_ofs = pericfg_rst_ofs,
.rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs),
},
};

6
drivers/clk/mediatek/clk-mt7622-eth.c
View File

@ -65,10 +65,12 @@ static const struct mtk_gate sgmii_clks[] = {
"ssusb_cdr_fb", 5),
};
static u16 rst_ofs[] = { 0x34, };
static const struct mtk_clk_rst_desc clk_rst_desc = {
.version = MTK_RST_SIMPLE,
.rst_bank_nr = 1,
.reg_ofs = 0x34,
.rst_bank_ofs = rst_ofs,
.rst_bank_nr = ARRAY_SIZE(rst_ofs),
};
static int clk_mt7622_ethsys_init(struct platform_device *pdev)

6
drivers/clk/mediatek/clk-mt7622-hif.c
View File

@ -76,10 +76,12 @@ static const struct mtk_gate pcie_clks[] = {
GATE_PCIE(CLK_SATA_PM_EN, "sata_pm_en", "univpll2_d4", 30),
};
static u16 rst_ofs[] = { 0x34, };
static const struct mtk_clk_rst_desc clk_rst_desc = {
.version = MTK_RST_SIMPLE,
.rst_bank_nr = 1,
.reg_ofs = 0x34,
.rst_bank_ofs = rst_ofs,
.rst_bank_nr = ARRAY_SIZE(rst_ofs),
};
static int clk_mt7622_ssusbsys_init(struct platform_device *pdev)

11
drivers/clk/mediatek/clk-mt7622.c
View File

@ -610,18 +610,21 @@ static struct mtk_composite peri_muxes[] = {
MUX(CLK_PERIBUS_SEL, "peribus_ck_sel", peribus_ck_parents, 0x05C, 0, 1),
};
static u16 infrasys_rst_ofs[] = { 0x30, };
static u16 pericfg_rst_ofs[] = { 0x0, 0x4, };
static const struct mtk_clk_rst_desc clk_rst_desc[] = {
/* infrasys */
{
.version = MTK_RST_SIMPLE,
.rst_bank_nr = 1,
.reg_ofs = 0x30,
.rst_bank_ofs = infrasys_rst_ofs,
.rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs),
},
/* pericfg */
{
.version = MTK_RST_SIMPLE,
.rst_bank_nr = 2,
.reg_ofs = 0x0,
.rst_bank_ofs = pericfg_rst_ofs,
.rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs),
},
};

6
drivers/clk/mediatek/clk-mt7629-eth.c
View File

@ -76,10 +76,12 @@ static const struct mtk_gate sgmii_clks[2][4] = {
}
};
static u16 rst_ofs[] = { 0x34, };
static const struct mtk_clk_rst_desc clk_rst_desc = {
.version = MTK_RST_SIMPLE,
.rst_bank_nr = 1,
.reg_ofs = 0x34,
.rst_bank_ofs = rst_ofs,
.rst_bank_nr = ARRAY_SIZE(rst_ofs),
};
static int clk_mt7629_ethsys_init(struct platform_device *pdev)

6
drivers/clk/mediatek/clk-mt7629-hif.c
View File

@ -71,10 +71,12 @@ static const struct mtk_gate pcie_clks[] = {
GATE_PCIE(CLK_PCIE_P0_PIPE_EN, "pcie_p0_pipe_en", "pcie0_pipe_en", 23),
};
static u16 rst_ofs[] = { 0x34, };
static const struct mtk_clk_rst_desc clk_rst_desc = {
.version = MTK_RST_SIMPLE,
.rst_bank_nr = 1,
.reg_ofs = 0x34,
.rst_bank_ofs = rst_ofs,
.rst_bank_nr = ARRAY_SIZE(rst_ofs),
};
static int clk_mt7629_ssusbsys_init(struct platform_device *pdev)

11
drivers/clk/mediatek/clk-mt8135.c
View File

@ -514,18 +514,21 @@ static const struct mtk_composite peri_clks[] __initconst = {
MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents, 0x40c, 3, 1),
};
static u16 infrasys_rst_ofs[] = { 0x30, 0x34, };
static u16 pericfg_rst_ofs[] = { 0x0, 0x4, };
static const struct mtk_clk_rst_desc clk_rst_desc[] = {
/* infrasys */
{
.version = MTK_RST_SIMPLE,
.rst_bank_nr = 2,
.reg_ofs = 0x30,
.rst_bank_ofs = infrasys_rst_ofs,
.rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs),
},
/* pericfg */
{
.version = MTK_RST_SIMPLE,
.rst_bank_nr = 2,
.reg_ofs = 0x0,
.rst_bank_ofs = pericfg_rst_ofs,
.rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs),
}
};

11
drivers/clk/mediatek/clk-mt8173.c
View File

@ -819,18 +819,21 @@ static const struct mtk_gate venclt_clks[] __initconst = {
GATE_VENCLT(CLK_VENCLT_CKE1, "venclt_cke1", "venclt_sel", 4),
};
static u16 infrasys_rst_ofs[] = { 0x30, 0x34, };
static u16 pericfg_rst_ofs[] = { 0x0, 0x4, };
static const struct mtk_clk_rst_desc clk_rst_desc[] = {
/* infrasys */
{
.version = MTK_RST_SIMPLE,
.rst_bank_nr = 2,
.reg_ofs = 0x30,
.rst_bank_ofs = infrasys_rst_ofs,
.rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs),
},
/* pericfg */
{
.version = MTK_RST_SIMPLE,
.rst_bank_nr = 2,
.reg_ofs = 0x0,
.rst_bank_ofs = pericfg_rst_ofs,
.rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs),
}
};

14
drivers/clk/mediatek/clk-mt8183.c
View File

@ -20,6 +20,9 @@
/* Infra global controller reset set register */
#define INFRA_RST0_SET_OFFSET 0x120
#define INFRA_RST1_SET_OFFSET 0x130
#define INFRA_RST2_SET_OFFSET 0x140
#define INFRA_RST3_SET_OFFSET 0x150
static DEFINE_SPINLOCK(mt8183_clk_lock);
@ -1153,10 +1156,17 @@ static const struct mtk_pll_data plls[] = {
0, 0, 32, 8, 0x02B4, 1, 0x02BC, 0x0014, 1, 0x02B8, 0, 0x02B4),
};
static u16 infra_rst_ofs[] = {
INFRA_RST0_SET_OFFSET,
INFRA_RST1_SET_OFFSET,
INFRA_RST2_SET_OFFSET,
INFRA_RST3_SET_OFFSET,
};
static const struct mtk_clk_rst_desc clk_rst_desc = {
.version = MTK_RST_SET_CLR,
.rst_bank_nr = 4,
.reg_ofs = INFRA_RST0_SET_OFFSET,
.rst_bank_ofs = infra_rst_ofs,
.rst_bank_nr = ARRAY_SIZE(infra_rst_ofs),
};
static int clk_mt8183_apmixed_probe(struct platform_device *pdev)

11
drivers/clk/mediatek/reset.c
View File

@ -24,8 +24,8 @@ static int mtk_reset_update(struct reset_controller_dev *rcdev,
unsigned int val = deassert ? 0 : ~0;
return regmap_update_bits(data->regmap,
data->desc->reg_ofs + ((id / 32) << 2),
BIT(id % 32), val);
data->desc->rst_bank_ofs[id / RST_NR_PER_BANK],
BIT(id % RST_NR_PER_BANK), val);
}
static int mtk_reset_assert(struct reset_controller_dev *rcdev,
@ -58,8 +58,9 @@ static int mtk_reset_update_set_clr(struct reset_controller_dev *rcdev,
unsigned int deassert_ofs = deassert ? 0x4 : 0;
return regmap_write(data->regmap,
data->desc->reg_ofs + ((id / 32) << 4) + deassert_ofs,
BIT(id % 32));
data->desc->rst_bank_ofs[id / RST_NR_PER_BANK] +
deassert_ofs,
BIT(id % RST_NR_PER_BANK));
}
static int mtk_reset_assert_set_clr(struct reset_controller_dev *rcdev,
@ -135,7 +136,7 @@ void mtk_register_reset_controller(struct device_node *np,
data->desc = desc;
data->regmap = regmap;
data->rcdev.owner = THIS_MODULE;
data->rcdev.nr_resets = desc->rst_bank_nr * 32;
data->rcdev.nr_resets = desc->rst_bank_nr * RST_NR_PER_BANK;
data->rcdev.ops = rcops;
data->rcdev.of_node = np;

6
drivers/clk/mediatek/reset.h
View File

@ -9,6 +9,8 @@
#include <linux/reset-controller.h>
#include <linux/types.h>
#define RST_NR_PER_BANK 32
/**
* enum mtk_reset_version - Version of MediaTek clock reset controller.
* @MTK_RST_SIMPLE: Use the same registers for bit set and clear.
@ -24,12 +26,12 @@ enum mtk_reset_version {
/**
* struct mtk_clk_rst_desc - Description of MediaTek clock reset.
* @version: Reset version which is defined in enum mtk_reset_version.
* @reg_ofs: Base offset of the reset register.
* @rst_bank_ofs: Pointer to an array containing base offsets of the reset register.
* @rst_bank_nr: Quantity of reset bank.
*/
struct mtk_clk_rst_desc {
enum mtk_reset_version version;
u16 reg_ofs;
u16 *rst_bank_ofs;
u32 rst_bank_nr;
};