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Pin control fixes for the v5.5 kernel cycle:

Browse Source 
- A host of fixes for the Intel baytrail and cherryview:
   properly serialize all register accesses and add the irqchip
   with the gpiochip as we need to, fix some pin lists and
   initialize the hardware in the right order.
 - Fix the Aspeed G6 LPC configuration.
 - Handle a possible NULL pointer exception in the core.
 - Fix the Kconfig dependencies for the Equilibrium driver.
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Merge tag 'pinctrl-v5.5-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control fixes from Linus Walleij:
 "Sorry that this fixes pull request took a while. Too much christmas
  business going on.

  This contains a few really important Intel fixes and some odd fixes:

   - A host of fixes for the Intel baytrail and cherryview: properly
     serialize all register accesses and add the irqchip with the
     gpiochip as we need to, fix some pin lists and initialize the
     hardware in the right order.

   - Fix the Aspeed G6 LPC configuration.

   - Handle a possible NULL pointer exception in the core.

   - Fix the Kconfig dependencies for the Equilibrium driver"

* tag 'pinctrl-v5.5-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
  pinctrl: ingenic: Fixup PIN_CONFIG_OUTPUT config
  pinctrl: Modify Kconfig to fix linker error
  pinctrl: pinmux: fix a possible null pointer in pinmux_can_be_used_for_gpio
  pinctrl: aspeed-g6: Fix LPC/eSPI mux configuration
  pinctrl: cherryview: Pass irqchip when adding gpiochip
  pinctrl: cherryview: Add GPIO <-> pin mapping ranges via callback
  pinctrl: cherryview: Split out irq hw-init into a separate helper function
  pinctrl: baytrail: Pass irqchip when adding gpiochip
  pinctrl: baytrail: Add GPIO <-> pin mapping ranges via callback
  pinctrl: baytrail: Update North Community pin list
  pinctrl: baytrail: Really serialize all register accesses
This commit is contained in:
Linus Torvalds 2019-12-20 09:49:05 -08:00
commit 7190a23a58
6 changed files with 189 additions and 157 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/pinctrl/Kconfig
View File

@ -422,6 +422,7 @@ config PINCTRL_TB10X
config PINCTRL_EQUILIBRIUM
tristate "Generic pinctrl and GPIO driver for Intel Lightning Mountain SoC"
depends on OF && HAS_IOMEM
select PINMUX
select PINCONF
select GPIOLIB

24
drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c
View File

@ -1088,60 +1088,52 @@ SSSF_PIN_DECL(AF15, GPIOV7, LPCSMI, SIG_DESC_SET(SCU434, 15));
#define AB7 176
SIG_EXPR_LIST_DECL_SESG(AB7, LAD0, LPC, SIG_DESC_SET(SCU434, 16),
SIG_DESC_CLEAR(SCU510, 6));
SIG_EXPR_LIST_DECL_SESG(AB7, ESPID0, ESPI, SIG_DESC_SET(SCU434, 16),
SIG_DESC_SET(SCU510, 6));
SIG_EXPR_LIST_DECL_SESG(AB7, ESPID0, ESPI, SIG_DESC_SET(SCU434, 16));
PIN_DECL_2(AB7, GPIOW0, LAD0, ESPID0);
#define AB8 177
SIG_EXPR_LIST_DECL_SESG(AB8, LAD1, LPC, SIG_DESC_SET(SCU434, 17),
SIG_DESC_CLEAR(SCU510, 6));
SIG_EXPR_LIST_DECL_SESG(AB8, ESPID1, ESPI, SIG_DESC_SET(SCU434, 17),
SIG_DESC_SET(SCU510, 6));
SIG_EXPR_LIST_DECL_SESG(AB8, ESPID1, ESPI, SIG_DESC_SET(SCU434, 17));
PIN_DECL_2(AB8, GPIOW1, LAD1, ESPID1);
#define AC8 178
SIG_EXPR_LIST_DECL_SESG(AC8, LAD2, LPC, SIG_DESC_SET(SCU434, 18),
SIG_DESC_CLEAR(SCU510, 6));
SIG_EXPR_LIST_DECL_SESG(AC8, ESPID2, ESPI, SIG_DESC_SET(SCU434, 18),
SIG_DESC_SET(SCU510, 6));
SIG_EXPR_LIST_DECL_SESG(AC8, ESPID2, ESPI, SIG_DESC_SET(SCU434, 18));
PIN_DECL_2(AC8, GPIOW2, LAD2, ESPID2);
#define AC7 179
SIG_EXPR_LIST_DECL_SESG(AC7, LAD3, LPC, SIG_DESC_SET(SCU434, 19),
SIG_DESC_CLEAR(SCU510, 6));
SIG_EXPR_LIST_DECL_SESG(AC7, ESPID3, ESPI, SIG_DESC_SET(SCU434, 19),
SIG_DESC_SET(SCU510, 6));
SIG_EXPR_LIST_DECL_SESG(AC7, ESPID3, ESPI, SIG_DESC_SET(SCU434, 19));
PIN_DECL_2(AC7, GPIOW3, LAD3, ESPID3);
#define AE7 180
SIG_EXPR_LIST_DECL_SESG(AE7, LCLK, LPC, SIG_DESC_SET(SCU434, 20),
SIG_DESC_CLEAR(SCU510, 6));
SIG_EXPR_LIST_DECL_SESG(AE7, ESPICK, ESPI, SIG_DESC_SET(SCU434, 20),
SIG_DESC_SET(SCU510, 6));
SIG_EXPR_LIST_DECL_SESG(AE7, ESPICK, ESPI, SIG_DESC_SET(SCU434, 20));
PIN_DECL_2(AE7, GPIOW4, LCLK, ESPICK);
#define AF7 181
SIG_EXPR_LIST_DECL_SESG(AF7, LFRAME, LPC, SIG_DESC_SET(SCU434, 21),
SIG_DESC_CLEAR(SCU510, 6));
SIG_EXPR_LIST_DECL_SESG(AF7, ESPICS, ESPI, SIG_DESC_SET(SCU434, 21),
SIG_DESC_SET(SCU510, 6));
SIG_EXPR_LIST_DECL_SESG(AF7, ESPICS, ESPI, SIG_DESC_SET(SCU434, 21));
PIN_DECL_2(AF7, GPIOW5, LFRAME, ESPICS);
#define AD7 182
SIG_EXPR_LIST_DECL_SESG(AD7, LSIRQ, LSIRQ, SIG_DESC_SET(SCU434, 22),
SIG_DESC_CLEAR(SCU510, 6));
SIG_EXPR_LIST_DECL_SESG(AD7, ESPIALT, ESPIALT, SIG_DESC_SET(SCU434, 22),
SIG_DESC_SET(SCU510, 6));
SIG_EXPR_LIST_DECL_SESG(AD7, ESPIALT, ESPIALT, SIG_DESC_SET(SCU434, 22));
PIN_DECL_2(AD7, GPIOW6, LSIRQ, ESPIALT);
FUNC_GROUP_DECL(LSIRQ, AD7);
FUNC_GROUP_DECL(ESPIALT, AD7);
#define AD8 183
SIG_EXPR_LIST_DECL_SESG(AD8, LPCRST, LPC, SIG_DESC_SET(SCU434, 23),
SIG_DESC_CLEAR(SCU510, 6));
SIG_EXPR_LIST_DECL_SESG(AD8, ESPIRST, ESPI, SIG_DESC_SET(SCU434, 23),
SIG_DESC_SET(SCU510, 6));
SIG_EXPR_LIST_DECL_SESG(AD8, ESPIRST, ESPI, SIG_DESC_SET(SCU434, 23));
PIN_DECL_2(AD8, GPIOW7, LPCRST, ESPIRST);
FUNC_GROUP_DECL(LPC, AB7, AB8, AC8, AC7, AE7, AF7, AD8);

200
drivers/pinctrl/intel/pinctrl-baytrail.c
View File

@ -110,7 +110,6 @@ struct byt_gpio {
struct platform_device *pdev;
struct pinctrl_dev *pctl_dev;
struct pinctrl_desc pctl_desc;
raw_spinlock_t lock;
const struct intel_pinctrl_soc_data *soc_data;
struct intel_community *communities_copy;
struct byt_gpio_pin_context *saved_context;
@ -494,34 +493,34 @@ static const struct intel_pinctrl_soc_data byt_sus_soc_data = {
};
static const struct pinctrl_pin_desc byt_ncore_pins[] = {
PINCTRL_PIN(0, "GPIO_NCORE0"),
PINCTRL_PIN(1, "GPIO_NCORE1"),
PINCTRL_PIN(2, "GPIO_NCORE2"),
PINCTRL_PIN(3, "GPIO_NCORE3"),
PINCTRL_PIN(4, "GPIO_NCORE4"),
PINCTRL_PIN(5, "GPIO_NCORE5"),
PINCTRL_PIN(6, "GPIO_NCORE6"),
PINCTRL_PIN(7, "GPIO_NCORE7"),
PINCTRL_PIN(8, "GPIO_NCORE8"),
PINCTRL_PIN(9, "GPIO_NCORE9"),
PINCTRL_PIN(10, "GPIO_NCORE10"),
PINCTRL_PIN(11, "GPIO_NCORE11"),
PINCTRL_PIN(12, "GPIO_NCORE12"),
PINCTRL_PIN(13, "GPIO_NCORE13"),
PINCTRL_PIN(14, "GPIO_NCORE14"),
PINCTRL_PIN(15, "GPIO_NCORE15"),
PINCTRL_PIN(16, "GPIO_NCORE16"),
PINCTRL_PIN(17, "GPIO_NCORE17"),
PINCTRL_PIN(18, "GPIO_NCORE18"),
PINCTRL_PIN(19, "GPIO_NCORE19"),
PINCTRL_PIN(20, "GPIO_NCORE20"),
PINCTRL_PIN(21, "GPIO_NCORE21"),
PINCTRL_PIN(22, "GPIO_NCORE22"),
PINCTRL_PIN(23, "GPIO_NCORE23"),
PINCTRL_PIN(24, "GPIO_NCORE24"),
PINCTRL_PIN(25, "GPIO_NCORE25"),
PINCTRL_PIN(26, "GPIO_NCORE26"),
PINCTRL_PIN(27, "GPIO_NCORE27"),
PINCTRL_PIN(0, "HV_DDI0_HPD"),
PINCTRL_PIN(1, "HV_DDI0_DDC_SDA"),
PINCTRL_PIN(2, "HV_DDI0_DDC_SCL"),
PINCTRL_PIN(3, "PANEL0_VDDEN"),
PINCTRL_PIN(4, "PANEL0_BKLTEN"),
PINCTRL_PIN(5, "PANEL0_BKLTCTL"),
PINCTRL_PIN(6, "HV_DDI1_HPD"),
PINCTRL_PIN(7, "HV_DDI1_DDC_SDA"),
PINCTRL_PIN(8, "HV_DDI1_DDC_SCL"),
PINCTRL_PIN(9, "PANEL1_VDDEN"),
PINCTRL_PIN(10, "PANEL1_BKLTEN"),
PINCTRL_PIN(11, "PANEL1_BKLTCTL"),
PINCTRL_PIN(12, "GP_INTD_DSI_TE1"),
PINCTRL_PIN(13, "HV_DDI2_DDC_SDA"),
PINCTRL_PIN(14, "HV_DDI2_DDC_SCL"),
PINCTRL_PIN(15, "GP_CAMERASB00"),
PINCTRL_PIN(16, "GP_CAMERASB01"),
PINCTRL_PIN(17, "GP_CAMERASB02"),
PINCTRL_PIN(18, "GP_CAMERASB03"),
PINCTRL_PIN(19, "GP_CAMERASB04"),
PINCTRL_PIN(20, "GP_CAMERASB05"),
PINCTRL_PIN(21, "GP_CAMERASB06"),
PINCTRL_PIN(22, "GP_CAMERASB07"),
PINCTRL_PIN(23, "GP_CAMERASB08"),
PINCTRL_PIN(24, "GP_CAMERASB09"),
PINCTRL_PIN(25, "GP_CAMERASB10"),
PINCTRL_PIN(26, "GP_CAMERASB11"),
PINCTRL_PIN(27, "GP_INTD_DSI_TE2"),
};
static const unsigned int byt_ncore_pins_map[BYT_NGPIO_NCORE] = {
@ -549,6 +548,8 @@ static const struct intel_pinctrl_soc_data *byt_soc_data[] = {
NULL
};
static DEFINE_RAW_SPINLOCK(byt_lock);
static struct intel_community *byt_get_community(struct byt_gpio *vg,
unsigned int pin)
{
@ -658,7 +659,7 @@ static void byt_set_group_simple_mux(struct byt_gpio *vg,
unsigned long flags;
int i;
raw_spin_lock_irqsave(&vg->lock, flags);
raw_spin_lock_irqsave(&byt_lock, flags);
for (i = 0; i < group.npins; i++) {
void __iomem *padcfg0;
@ -678,7 +679,7 @@ static void byt_set_group_simple_mux(struct byt_gpio *vg,
writel(value, padcfg0);
}
raw_spin_unlock_irqrestore(&vg->lock, flags);
raw_spin_unlock_irqrestore(&byt_lock, flags);
}
static void byt_set_group_mixed_mux(struct byt_gpio *vg,
@ -688,7 +689,7 @@ static void byt_set_group_mixed_mux(struct byt_gpio *vg,
unsigned long flags;
int i;
raw_spin_lock_irqsave(&vg->lock, flags);
raw_spin_lock_irqsave(&byt_lock, flags);
for (i = 0; i < group.npins; i++) {
void __iomem *padcfg0;
@ -708,7 +709,7 @@ static void byt_set_group_mixed_mux(struct byt_gpio *vg,
writel(value, padcfg0);
}
raw_spin_unlock_irqrestore(&vg->lock, flags);
raw_spin_unlock_irqrestore(&byt_lock, flags);
}
static int byt_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector,
@ -749,11 +750,11 @@ static void byt_gpio_clear_triggering(struct byt_gpio *vg, unsigned int offset)
unsigned long flags;
u32 value;
raw_spin_lock_irqsave(&vg->lock, flags);
raw_spin_lock_irqsave(&byt_lock, flags);
value = readl(reg);
value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL);
writel(value, reg);
raw_spin_unlock_irqrestore(&vg->lock, flags);
raw_spin_unlock_irqrestore(&byt_lock, flags);
}
static int byt_gpio_request_enable(struct pinctrl_dev *pctl_dev,
@ -765,7 +766,7 @@ static int byt_gpio_request_enable(struct pinctrl_dev *pctl_dev,
u32 value, gpio_mux;
unsigned long flags;
raw_spin_lock_irqsave(&vg->lock, flags);
raw_spin_lock_irqsave(&byt_lock, flags);
/*
* In most cases, func pin mux 000 means GPIO function.
@ -787,7 +788,7 @@ static int byt_gpio_request_enable(struct pinctrl_dev *pctl_dev,
"pin %u forcibly re-configured as GPIO\n", offset);
}
raw_spin_unlock_irqrestore(&vg->lock, flags);
raw_spin_unlock_irqrestore(&byt_lock, flags);
pm_runtime_get(&vg->pdev->dev);
@ -815,7 +816,7 @@ static int byt_gpio_set_direction(struct pinctrl_dev *pctl_dev,
unsigned long flags;
u32 value;
raw_spin_lock_irqsave(&vg->lock, flags);
raw_spin_lock_irqsave(&byt_lock, flags);
value = readl(val_reg);
value &= ~BYT_DIR_MASK;
@ -832,7 +833,7 @@ static int byt_gpio_set_direction(struct pinctrl_dev *pctl_dev,
"Potential Error: Setting GPIO with direct_irq_en to output");
writel(value, val_reg);
raw_spin_unlock_irqrestore(&vg->lock, flags);
raw_spin_unlock_irqrestore(&byt_lock, flags);
return 0;
}
@ -901,11 +902,11 @@ static int byt_pin_config_get(struct pinctrl_dev *pctl_dev, unsigned int offset,
u32 conf, pull, val, debounce;
u16 arg = 0;
raw_spin_lock_irqsave(&vg->lock, flags);
raw_spin_lock_irqsave(&byt_lock, flags);
conf = readl(conf_reg);
pull = conf & BYT_PULL_ASSIGN_MASK;
val = readl(val_reg);
raw_spin_unlock_irqrestore(&vg->lock, flags);
raw_spin_unlock_irqrestore(&byt_lock, flags);
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
@ -932,9 +933,9 @@ static int byt_pin_config_get(struct pinctrl_dev *pctl_dev, unsigned int offset,
if (!(conf & BYT_DEBOUNCE_EN))
return -EINVAL;
raw_spin_lock_irqsave(&vg->lock, flags);
raw_spin_lock_irqsave(&byt_lock, flags);
debounce = readl(db_reg);
raw_spin_unlock_irqrestore(&vg->lock, flags);
raw_spin_unlock_irqrestore(&byt_lock, flags);
switch (debounce & BYT_DEBOUNCE_PULSE_MASK) {
case BYT_DEBOUNCE_PULSE_375US:
@ -986,7 +987,7 @@ static int byt_pin_config_set(struct pinctrl_dev *pctl_dev,
u32 conf, val, debounce;
int i, ret = 0;
raw_spin_lock_irqsave(&vg->lock, flags);
raw_spin_lock_irqsave(&byt_lock, flags);
conf = readl(conf_reg);
val = readl(val_reg);
@ -1094,7 +1095,7 @@ static int byt_pin_config_set(struct pinctrl_dev *pctl_dev,
if (!ret)
writel(conf, conf_reg);
raw_spin_unlock_irqrestore(&vg->lock, flags);
raw_spin_unlock_irqrestore(&byt_lock, flags);
return ret;
}
@ -1119,9 +1120,9 @@ static int byt_gpio_get(struct gpio_chip *chip, unsigned int offset)
unsigned long flags;
u32 val;
raw_spin_lock_irqsave(&vg->lock, flags);
raw_spin_lock_irqsave(&byt_lock, flags);
val = readl(reg);
raw_spin_unlock_irqrestore(&vg->lock, flags);
raw_spin_unlock_irqrestore(&byt_lock, flags);
return !!(val & BYT_LEVEL);
}
@ -1136,13 +1137,13 @@ static void byt_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
if (!reg)
return;
raw_spin_lock_irqsave(&vg->lock, flags);
raw_spin_lock_irqsave(&byt_lock, flags);
old_val = readl(reg);
if (value)
writel(old_val | BYT_LEVEL, reg);
else
writel(old_val & ~BYT_LEVEL, reg);
raw_spin_unlock_irqrestore(&vg->lock, flags);
raw_spin_unlock_irqrestore(&byt_lock, flags);
}
static int byt_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
@ -1155,9 +1156,9 @@ static int byt_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
if (!reg)
return -EINVAL;
raw_spin_lock_irqsave(&vg->lock, flags);
raw_spin_lock_irqsave(&byt_lock, flags);
value = readl(reg);
raw_spin_unlock_irqrestore(&vg->lock, flags);
raw_spin_unlock_irqrestore(&byt_lock, flags);
if (!(value & BYT_OUTPUT_EN))
return 0;
@ -1200,14 +1201,14 @@ static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
const char *label;
unsigned int pin;
raw_spin_lock_irqsave(&vg->lock, flags);
raw_spin_lock_irqsave(&byt_lock, flags);
pin = vg->soc_data->pins[i].number;
reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
if (!reg) {
seq_printf(s,
"Could not retrieve pin %i conf0 reg\n",
pin);
raw_spin_unlock_irqrestore(&vg->lock, flags);
raw_spin_unlock_irqrestore(&byt_lock, flags);
continue;
}
conf0 = readl(reg);
@ -1216,11 +1217,11 @@ static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
if (!reg) {
seq_printf(s,
"Could not retrieve pin %i val reg\n", pin);
raw_spin_unlock_irqrestore(&vg->lock, flags);
raw_spin_unlock_irqrestore(&byt_lock, flags);
continue;
}
val = readl(reg);
raw_spin_unlock_irqrestore(&vg->lock, flags);
raw_spin_unlock_irqrestore(&byt_lock, flags);
comm = byt_get_community(vg, pin);
if (!comm) {
@ -1304,9 +1305,9 @@ static void byt_irq_ack(struct irq_data *d)
if (!reg)
return;
raw_spin_lock(&vg->lock);
raw_spin_lock(&byt_lock);
writel(BIT(offset % 32), reg);
raw_spin_unlock(&vg->lock);
raw_spin_unlock(&byt_lock);
}
static void byt_irq_mask(struct irq_data *d)
@ -1330,7 +1331,7 @@ static void byt_irq_unmask(struct irq_data *d)
if (!reg)
return;
raw_spin_lock_irqsave(&vg->lock, flags);
raw_spin_lock_irqsave(&byt_lock, flags);
value = readl(reg);
switch (irqd_get_trigger_type(d)) {
@ -1353,7 +1354,7 @@ static void byt_irq_unmask(struct irq_data *d)
writel(value, reg);
raw_spin_unlock_irqrestore(&vg->lock, flags);
raw_spin_unlock_irqrestore(&byt_lock, flags);
}
static int byt_irq_type(struct irq_data *d, unsigned int type)
@ -1367,7 +1368,7 @@ static int byt_irq_type(struct irq_data *d, unsigned int type)
if (!reg || offset >= vg->chip.ngpio)
return -EINVAL;
raw_spin_lock_irqsave(&vg->lock, flags);
raw_spin_lock_irqsave(&byt_lock, flags);
value = readl(reg);
WARN(value & BYT_DIRECT_IRQ_EN,
@ -1389,7 +1390,7 @@ static int byt_irq_type(struct irq_data *d, unsigned int type)
else if (type & IRQ_TYPE_LEVEL_MASK)
irq_set_handler_locked(d, handle_level_irq);
raw_spin_unlock_irqrestore(&vg->lock, flags);
raw_spin_unlock_irqrestore(&byt_lock, flags);
return 0;
}
@ -1425,9 +1426,9 @@ static void byt_gpio_irq_handler(struct irq_desc *desc)
continue;
}
raw_spin_lock(&vg->lock);
raw_spin_lock(&byt_lock);
pending = readl(reg);
raw_spin_unlock(&vg->lock);
raw_spin_unlock(&byt_lock);
for_each_set_bit(pin, &pending, 32) {
virq = irq_find_mapping(vg->chip.irq.domain, base + pin);
generic_handle_irq(virq);
@ -1450,9 +1451,9 @@ static void byt_init_irq_valid_mask(struct gpio_chip *chip,
*/
}
static void byt_gpio_irq_init_hw(struct byt_gpio *vg)
static int byt_gpio_irq_init_hw(struct gpio_chip *chip)
{
struct gpio_chip *gc = &vg->chip;
struct byt_gpio *vg = gpiochip_get_data(chip);
struct device *dev = &vg->pdev->dev;
void __iomem *reg;
u32 base, value;
@ -1476,7 +1477,7 @@ static void byt_gpio_irq_init_hw(struct byt_gpio *vg)
value = readl(reg);
if (value & BYT_DIRECT_IRQ_EN) {
clear_bit(i, gc->irq.valid_mask);
clear_bit(i, chip->irq.valid_mask);
dev_dbg(dev, "excluding GPIO %d from IRQ domain\n", i);
} else if ((value & BYT_PIN_MUX) == byt_get_gpio_mux(vg, i)) {
byt_gpio_clear_triggering(vg, i);
@ -1504,6 +1505,21 @@ static void byt_gpio_irq_init_hw(struct byt_gpio *vg)
"GPIO interrupt error, pins misconfigured. INT_STAT%u: 0x%08x\n",
base / 32, value);
}
return 0;
}
static int byt_gpio_add_pin_ranges(struct gpio_chip *chip)
{
struct byt_gpio *vg = gpiochip_get_data(chip);
struct device *dev = &vg->pdev->dev;
int ret;
ret = gpiochip_add_pin_range(chip, dev_name(dev), 0, 0, vg->soc_data->npins);
if (ret)
dev_err(dev, "failed to add GPIO pin range\n");
return ret;
}
static int byt_gpio_probe(struct byt_gpio *vg)
@ -1518,6 +1534,7 @@ static int byt_gpio_probe(struct byt_gpio *vg)
gc->label = dev_name(&vg->pdev->dev);
gc->base = -1;
gc->can_sleep = false;
gc->add_pin_ranges = byt_gpio_add_pin_ranges;
gc->parent = &vg->pdev->dev;
gc->ngpio = vg->soc_data->npins;
gc->irq.init_valid_mask = byt_init_irq_valid_mask;
@ -1528,33 +1545,30 @@ static int byt_gpio_probe(struct byt_gpio *vg)
if (!vg->saved_context)
return -ENOMEM;
#endif
ret = devm_gpiochip_add_data(&vg->pdev->dev, gc, vg);
if (ret) {
dev_err(&vg->pdev->dev, "failed adding byt-gpio chip\n");
return ret;
}
ret = gpiochip_add_pin_range(&vg->chip, dev_name(&vg->pdev->dev),
0, 0, vg->soc_data->npins);
if (ret) {
dev_err(&vg->pdev->dev, "failed to add GPIO pin range\n");
return ret;
}
/* set up interrupts */
irq_rc = platform_get_resource(vg->pdev, IORESOURCE_IRQ, 0);
if (irq_rc && irq_rc->start) {
byt_gpio_irq_init_hw(vg);
ret = gpiochip_irqchip_add(gc, &byt_irqchip, 0,
handle_bad_irq, IRQ_TYPE_NONE);
if (ret) {
dev_err(&vg->pdev->dev, "failed to add irqchip\n");
return ret;
}
struct gpio_irq_chip *girq;
gpiochip_set_chained_irqchip(gc, &byt_irqchip,
(unsigned)irq_rc->start,
byt_gpio_irq_handler);
girq = &gc->irq;
girq->chip = &byt_irqchip;
girq->init_hw = byt_gpio_irq_init_hw;
girq->parent_handler = byt_gpio_irq_handler;
girq->num_parents = 1;
girq->parents = devm_kcalloc(&vg->pdev->dev, girq->num_parents,
sizeof(*girq->parents), GFP_KERNEL);
if (!girq->parents)
return -ENOMEM;
girq->parents[0] = (unsigned int)irq_rc->start;
girq->default_type = IRQ_TYPE_NONE;
girq->handler = handle_bad_irq;
}
ret = devm_gpiochip_add_data(&vg->pdev->dev, gc, vg);
if (ret) {
dev_err(&vg->pdev->dev, "failed adding byt-gpio chip\n");
return ret;
}
return ret;
@ -1638,8 +1652,6 @@ static int byt_pinctrl_probe(struct platform_device *pdev)
return PTR_ERR(vg->pctl_dev);
}
raw_spin_lock_init(&vg->lock);
ret = byt_gpio_probe(vg);
if (ret)
return ret;
@ -1654,8 +1666,11 @@ static int byt_pinctrl_probe(struct platform_device *pdev)
static int byt_gpio_suspend(struct device *dev)
{
struct byt_gpio *vg = dev_get_drvdata(dev);
unsigned long flags;
int i;
raw_spin_lock_irqsave(&byt_lock, flags);
for (i = 0; i < vg->soc_data->npins; i++) {
void __iomem *reg;
u32 value;
@ -1676,14 +1691,18 @@ static int byt_gpio_suspend(struct device *dev)
vg->saved_context[i].val = value;
}
raw_spin_unlock_irqrestore(&byt_lock, flags);
return 0;
}
static int byt_gpio_resume(struct device *dev)
{
struct byt_gpio *vg = dev_get_drvdata(dev);
unsigned long flags;
int i;
raw_spin_lock_irqsave(&byt_lock, flags);
for (i = 0; i < vg->soc_data->npins; i++) {
void __iomem *reg;
u32 value;
@ -1721,6 +1740,7 @@ static int byt_gpio_resume(struct device *dev)
}
}
raw_spin_unlock_irqrestore(&byt_lock, flags);
return 0;
}
#endif

117
drivers/pinctrl/intel/pinctrl-cherryview.c
View File

@ -149,6 +149,7 @@ struct chv_pin_context {
* @chip: GPIO chip in this pin controller
* @irqchip: IRQ chip in this pin controller
* @regs: MMIO registers
* @irq: Our parent irq
* @intr_lines: Stores mapping between 16 HW interrupt wires and GPIO
* offset (in GPIO number space)
* @community: Community this pinctrl instance represents
@ -165,6 +166,7 @@ struct chv_pinctrl {
struct gpio_chip chip;
struct irq_chip irqchip;
void __iomem *regs;
unsigned int irq;
unsigned int intr_lines[16];
const struct chv_community *community;
u32 saved_intmask;
@ -1555,29 +1557,39 @@ static void chv_init_irq_valid_mask(struct gpio_chip *chip,
}
}
static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq)
static int chv_gpio_irq_init_hw(struct gpio_chip *chip)
{
const struct chv_gpio_pinrange *range;
struct gpio_chip *chip = &pctrl->chip;
bool need_valid_mask = !dmi_check_system(chv_no_valid_mask);
const struct chv_community *community = pctrl->community;
int ret, i, irq_base;
struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
*chip = chv_gpio_chip;
chip->ngpio = community->pins[community->npins - 1].number + 1;
chip->label = dev_name(pctrl->dev);
chip->parent = pctrl->dev;
chip->base = -1;
if (need_valid_mask)
chip->irq.init_valid_mask = chv_init_irq_valid_mask;
ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl);
if (ret) {
dev_err(pctrl->dev, "Failed to register gpiochip\n");
return ret;
/*
* The same set of machines in chv_no_valid_mask[] have incorrectly
* configured GPIOs that generate spurious interrupts so we use
* this same list to apply another quirk for them.
*
* See also https://bugzilla.kernel.org/show_bug.cgi?id=197953.
*/
if (!pctrl->chip.irq.init_valid_mask) {
/*
* Mask all interrupts the community is able to generate
* but leave the ones that can only generate GPEs unmasked.
*/
chv_writel(GENMASK(31, pctrl->community->nirqs),
pctrl->regs + CHV_INTMASK);
}
/* Clear all interrupts */
chv_writel(0xffff, pctrl->regs + CHV_INTSTAT);
return 0;
}
static int chv_gpio_add_pin_ranges(struct gpio_chip *chip)
{
struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
const struct chv_community *community = pctrl->community;
const struct chv_gpio_pinrange *range;
int ret, i;
for (i = 0; i < community->ngpio_ranges; i++) {
range = &community->gpio_ranges[i];
ret = gpiochip_add_pin_range(chip, dev_name(pctrl->dev),
@ -1589,34 +1601,26 @@ static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq)
}
}
/*
* The same set of machines in chv_no_valid_mask[] have incorrectly
* configured GPIOs that generate spurious interrupts so we use
* this same list to apply another quirk for them.
*
* See also https://bugzilla.kernel.org/show_bug.cgi?id=197953.
*/
if (!need_valid_mask) {
/*
* Mask all interrupts the community is able to generate
* but leave the ones that can only generate GPEs unmasked.
*/
chv_writel(GENMASK(31, pctrl->community->nirqs),
pctrl->regs + CHV_INTMASK);
}
return 0;
}
/* Clear all interrupts */
chv_writel(0xffff, pctrl->regs + CHV_INTSTAT);
static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq)
{
const struct chv_gpio_pinrange *range;
struct gpio_chip *chip = &pctrl->chip;
bool need_valid_mask = !dmi_check_system(chv_no_valid_mask);
const struct chv_community *community = pctrl->community;
int ret, i, irq_base;
if (!need_valid_mask) {
irq_base = devm_irq_alloc_descs(pctrl->dev, -1, 0,
community->npins, NUMA_NO_NODE);
if (irq_base < 0) {
dev_err(pctrl->dev, "Failed to allocate IRQ numbers\n");
return irq_base;
}
}
*chip = chv_gpio_chip;
chip->ngpio = community->pins[community->npins - 1].number + 1;
chip->label = dev_name(pctrl->dev);
chip->add_pin_ranges = chv_gpio_add_pin_ranges;
chip->parent = pctrl->dev;
chip->base = -1;
pctrl->irq = irq;
pctrl->irqchip.name = "chv-gpio";
pctrl->irqchip.irq_startup = chv_gpio_irq_startup;
pctrl->irqchip.irq_ack = chv_gpio_irq_ack;
@ -1625,10 +1629,27 @@ static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq)
pctrl->irqchip.irq_set_type = chv_gpio_irq_type;
pctrl->irqchip.flags = IRQCHIP_SKIP_SET_WAKE;
ret = gpiochip_irqchip_add(chip, &pctrl->irqchip, 0,
handle_bad_irq, IRQ_TYPE_NONE);
chip->irq.chip = &pctrl->irqchip;
chip->irq.init_hw = chv_gpio_irq_init_hw;
chip->irq.parent_handler = chv_gpio_irq_handler;
chip->irq.num_parents = 1;
chip->irq.parents = &pctrl->irq;
chip->irq.default_type = IRQ_TYPE_NONE;
chip->irq.handler = handle_bad_irq;
if (need_valid_mask) {
chip->irq.init_valid_mask = chv_init_irq_valid_mask;
} else {
irq_base = devm_irq_alloc_descs(pctrl->dev, -1, 0,
community->npins, NUMA_NO_NODE);
if (irq_base < 0) {
dev_err(pctrl->dev, "Failed to allocate IRQ numbers\n");
return irq_base;
}
}
ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl);
if (ret) {
dev_err(pctrl->dev, "failed to add IRQ chip\n");
dev_err(pctrl->dev, "Failed to register gpiochip\n");
return ret;
}
@ -1642,8 +1663,6 @@ static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq)
}
}
gpiochip_set_chained_irqchip(chip, &pctrl->irqchip, irq,
chv_gpio_irq_handler);
return 0;
}

2
drivers/pinctrl/pinctrl-ingenic.c
View File

@ -1809,7 +1809,7 @@ static void ingenic_set_bias(struct ingenic_pinctrl *jzpc,
static void ingenic_set_output_level(struct ingenic_pinctrl *jzpc,
unsigned int pin, bool high)
{
if (jzpc->version >= ID_JZ4770)
if (jzpc->version >= ID_JZ4760)
ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT0, high);
else
ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DATA, high);

2
drivers/pinctrl/pinmux.c
View File

@ -85,7 +85,7 @@ bool pinmux_can_be_used_for_gpio(struct pinctrl_dev *pctldev, unsigned pin)
const struct pinmux_ops *ops = pctldev->desc->pmxops;
/* Can't inspect pin, assume it can be used */
if (!desc)
if (!desc || !ops)
return true;
if (ops->strict && desc->mux_usecount)