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drm/amdgpu/gfx10: set tcp harvest for navi12

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Same as navi10.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Xiaojie Yuan 2019-01-29 22:36:15 +08:00 committed by Alex Deucher
parent 44e9e7c96c
commit 71745cf474
1 changed files with 5 additions and 3 deletions
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8
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
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@ -1567,7 +1567,7 @@ static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
u32 utcl_invreq_disable = 0; u32 utcl_invreq_disable = 0;
/* /*
* GCRD_TARGETS_DISABLE field contains * GCRD_TARGETS_DISABLE field contains
* for Navi10: GL1C=[18:15], SQC=[14:10], TCP=[9:0] * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0]
* for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0] * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0]
*/ */
u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask( u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask(
@ -1576,7 +1576,7 @@ static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
4); /* GL1C */ 4); /* GL1C */
/* /*
* UTCL1_UTCL0_INVREQ_DISABLE field contains * UTCL1_UTCL0_INVREQ_DISABLE field contains
* for Navi10: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0] * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0]
* for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0] * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0]
*/ */
u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask( u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask(
@ -1585,7 +1585,9 @@ static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
4 + /* RMI */ 4 + /* RMI */
1); /* SQG */ 1); /* SQG */
if (adev->asic_type == CHIP_NAVI10 || adev->asic_type == CHIP_NAVI14) { if (adev->asic_type == CHIP_NAVI10 ||
adev->asic_type == CHIP_NAVI14 ||
adev->asic_type == CHIP_NAVI12) {
mutex_lock(&adev->grbm_idx_mutex); mutex_lock(&adev->grbm_idx_mutex);
for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {