ASoC: max9867: Calculate LRCLK divider
Drop "Common NI Values Table" and calculate LRCLK divider, then add allowed rate constraints based on master clock frequency. Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Ladislav Michl
Mark Brown
parent
29f58ff067
commit
715ee1916b
@ -126,76 +126,98 @@ static const struct snd_soc_dapm_route max9867_audio_map[] = {
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{"LINE_IN", NULL, "Right Line"},
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};
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enum rates {
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pcm_rate_8, pcm_rate_16, pcm_rate_24,
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pcm_rate_32, pcm_rate_44,
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pcm_rate_48, max_pcm_rate,
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static const unsigned int max9867_rates_44k1[] = {
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11025, 22050, 44100,
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};
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static const struct ni_div_rates {
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u32 mclk;
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u16 ni[max_pcm_rate];
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} ni_div[] = {
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{11289600, {0x116A, 0x22D4, 0x343F, 0x45A9, 0x6000, 0x687D} },
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{12000000, {0x1062, 0x20C5, 0x3127, 0x4189, 0x5A51, 0x624E} },
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{12288000, {0x1000, 0x2000, 0x3000, 0x4000, 0x5833, 0x6000} },
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{13000000, {0x0F20, 0x1E3F, 0x2D5F, 0x3C7F, 0x535F, 0x5ABE} },
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{19200000, {0x0A3D, 0x147B, 0x1EB8, 0x28F6, 0x3873, 0x3D71} },
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{24000000, {0x1062, 0x20C5, 0x1893, 0x4189, 0x5A51, 0x624E} },
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{26000000, {0x0F20, 0x1E3F, 0x16AF, 0x3C7F, 0x535F, 0x5ABE} },
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{27000000, {0x0E90, 0x1D21, 0x15D8, 0x3A41, 0x5048, 0x5762} },
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static const struct snd_pcm_hw_constraint_list max9867_constraints_44k1 = {
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.list = max9867_rates_44k1,
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.count = ARRAY_SIZE(max9867_rates_44k1),
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};
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static inline int get_ni_value(int mclk, int rate)
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static const unsigned int max9867_rates_48k[] = {
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8000, 16000, 32000, 48000,
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};
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static const struct snd_pcm_hw_constraint_list max9867_constraints_48k = {
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.list = max9867_rates_48k,
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.count = ARRAY_SIZE(max9867_rates_48k),
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};
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struct max9867_priv {
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struct regmap *regmap;
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const struct snd_pcm_hw_constraint_list *constraints;
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unsigned int sysclk, pclk;
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bool master, dsp_a;
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};
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static int max9867_startup(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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int i, ret = 0;
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struct max9867_priv *max9867 =
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snd_soc_component_get_drvdata(dai->component);
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/* find the closest rate index*/
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for (i = 0; i < ARRAY_SIZE(ni_div); i++) {
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if (ni_div[i].mclk >= mclk)
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break;
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}
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if (i == ARRAY_SIZE(ni_div))
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return -EINVAL;
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if (max9867->constraints)
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snd_pcm_hw_constraint_list(substream->runtime, 0,
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SNDRV_PCM_HW_PARAM_RATE, max9867->constraints);
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switch (rate) {
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case 8000:
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return ni_div[i].ni[pcm_rate_8];
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case 16000:
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return ni_div[i].ni[pcm_rate_16];
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case 32000:
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return ni_div[i].ni[pcm_rate_32];
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case 44100:
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return ni_div[i].ni[pcm_rate_44];
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case 48000:
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return ni_div[i].ni[pcm_rate_48];
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default:
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pr_err("%s wrong rate %d\n", __func__, rate);
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ret = -EINVAL;
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}
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return ret;
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return 0;
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}
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static int max9867_dai_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
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{
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int value;
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unsigned long int rate, ratio;
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struct snd_soc_component *component = dai->component;
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struct max9867_priv *max9867 = snd_soc_component_get_drvdata(component);
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unsigned int ni_h, ni_l;
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int value;
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unsigned int ni = DIV_ROUND_CLOSEST_ULL(96ULL * 0x10000 * params_rate(params),
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max9867->pclk);
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value = get_ni_value(max9867->sysclk, params_rate(params));
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if (value < 0)
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return value;
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ni_h = (0xFF00 & value) >> 8;
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ni_l = 0x00FF & value;
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/* set up the ni value */
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regmap_update_bits(max9867->regmap, MAX9867_AUDIOCLKHIGH,
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MAX9867_NI_HIGH_MASK, ni_h);
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MAX9867_NI_HIGH_MASK, (0xFF00 & ni) >> 8);
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regmap_update_bits(max9867->regmap, MAX9867_AUDIOCLKLOW,
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MAX9867_NI_LOW_MASK, ni_l);
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if (!max9867->master) {
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MAX9867_NI_LOW_MASK, 0x00FF & ni);
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if (max9867->master) {
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if (max9867->dsp_a) {
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value = MAX9867_IFC1B_48X;
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} else {
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rate = params_rate(params) * 2 * params_width(params);
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ratio = max9867->pclk / rate;
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switch (params_width(params)) {
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case 8:
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case 16:
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switch (ratio) {
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case 2:
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value = MAX9867_IFC1B_PCLK_2;
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break;
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case 4:
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value = MAX9867_IFC1B_PCLK_4;
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break;
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case 8:
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value = MAX9867_IFC1B_PCLK_8;
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break;
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case 16:
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value = MAX9867_IFC1B_PCLK_16;
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break;
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default:
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return -EINVAL;
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}
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break;
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case 24:
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value = MAX9867_IFC1B_48X;
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break;
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case 32:
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value = MAX9867_IFC1B_64X;
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break;
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default:
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return -EINVAL;
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}
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}
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regmap_update_bits(max9867->regmap, MAX9867_IFC1B,
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MAX9867_IFC1B_BCLK_MASK, value);
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} else {
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/*
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* digital pll locks on to any externally supplied LRCLK signal
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* and also enable rapid lock mode.
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@ -204,46 +226,6 @@ static int max9867_dai_hw_params(struct snd_pcm_substream *substream,
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MAX9867_RAPID_LOCK, MAX9867_RAPID_LOCK);
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regmap_update_bits(max9867->regmap, MAX9867_AUDIOCLKHIGH,
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MAX9867_PLL, MAX9867_PLL);
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} else {
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unsigned long int bclk_rate, pclk_bclk_ratio;
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int bclk_value;
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bclk_rate = params_rate(params) * 2 * params_width(params);
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pclk_bclk_ratio = max9867->pclk/bclk_rate;
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switch (params_width(params)) {
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case 8:
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case 16:
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switch (pclk_bclk_ratio) {
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case 2:
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bclk_value = MAX9867_IFC1B_PCLK_2;
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break;
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case 4:
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bclk_value = MAX9867_IFC1B_PCLK_4;
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break;
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case 8:
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bclk_value = MAX9867_IFC1B_PCLK_8;
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break;
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case 16:
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bclk_value = MAX9867_IFC1B_PCLK_16;
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break;
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default:
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dev_err(component->dev,
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"unsupported sampling rate\n");
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return -EINVAL;
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}
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break;
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case 24:
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bclk_value = MAX9867_IFC1B_24BIT;
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break;
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case 32:
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bclk_value = MAX9867_IFC1B_32BIT;
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break;
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default:
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dev_err(component->dev, "unsupported sampling rate\n");
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return -EINVAL;
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}
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regmap_update_bits(max9867->regmap, MAX9867_IFC1B,
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MAX9867_IFC1B_BCLK_MASK, bclk_value);
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}
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return 0;
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}
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@ -285,8 +267,16 @@ static int max9867_set_dai_sysclk(struct snd_soc_dai *codec_dai,
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freq);
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return -EINVAL;
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}
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value = value << MAX9867_PSCLK_SHIFT;
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if (freq % 48000 == 0)
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max9867->constraints = &max9867_constraints_48k;
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else if (freq % 44100 == 0)
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max9867->constraints = &max9867_constraints_44k1;
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else
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dev_warn(component->dev,
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"Unable to set exact rate with %uHz clock frequency\n",
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freq);
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max9867->sysclk = freq;
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value = value << MAX9867_PSCLK_SHIFT;
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/* exact integer mode is not supported */
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value &= ~MAX9867_FREQ_MASK;
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regmap_update_bits(max9867->regmap, MAX9867_SYSCLK,
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@ -299,16 +289,17 @@ static int max9867_dai_set_fmt(struct snd_soc_dai *codec_dai,
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{
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struct snd_soc_component *component = codec_dai->component;
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struct max9867_priv *max9867 = snd_soc_component_get_drvdata(component);
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u8 iface1A = 0, iface1B = 0;
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u8 iface1A, iface1B;
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switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
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case SND_SOC_DAIFMT_CBM_CFM:
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max9867->master = 1;
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iface1A |= MAX9867_MASTER;
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max9867->master = true;
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iface1A = MAX9867_MASTER;
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iface1B = MAX9867_IFC1B_48X;
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break;
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case SND_SOC_DAIFMT_CBS_CFS:
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max9867->master = 0;
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iface1A &= ~MAX9867_MASTER;
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max9867->master = false;
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iface1A = iface1B = 0;
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break;
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default:
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return -EINVAL;
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@ -316,9 +307,11 @@ static int max9867_dai_set_fmt(struct snd_soc_dai *codec_dai,
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_I2S:
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max9867->dsp_a = false;
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iface1A |= MAX9867_I2S_DLY;
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break;
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case SND_SOC_DAIFMT_DSP_A:
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max9867->dsp_a = true;
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iface1A |= MAX9867_TDM_MODE | MAX9867_SDOUT_HIZ;
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break;
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default:
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@ -344,20 +337,18 @@ static int max9867_dai_set_fmt(struct snd_soc_dai *codec_dai,
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regmap_write(max9867->regmap, MAX9867_IFC1A, iface1A);
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regmap_write(max9867->regmap, MAX9867_IFC1B, iface1B);
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return 0;
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}
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static const struct snd_soc_dai_ops max9867_dai_ops = {
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.set_fmt = max9867_dai_set_fmt,
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.set_sysclk = max9867_set_dai_sysclk,
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.set_fmt = max9867_dai_set_fmt,
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.digital_mute = max9867_mute,
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.startup = max9867_startup,
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.hw_params = max9867_dai_hw_params,
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};
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#define MAX9867_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
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SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
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#define MAX9867_FORMATS (SNDRV_PCM_FMTBIT_S16_LE)
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static struct snd_soc_dai_driver max9867_dai[] = {
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{
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.name = "max9867-aif1",
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@ -365,15 +356,15 @@ static struct snd_soc_dai_driver max9867_dai[] = {
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.stream_name = "HiFi Playback",
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.channels_min = 2,
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.channels_max = 2,
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.rates = MAX9867_RATES,
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.formats = MAX9867_FORMATS,
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.rates = SNDRV_PCM_RATE_8000_48000,
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.formats = SNDRV_PCM_FMTBIT_S16_LE,
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},
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.capture = {
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.stream_name = "HiFi Capture",
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.channels_min = 2,
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.channels_max = 2,
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.rates = MAX9867_RATES,
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.formats = MAX9867_FORMATS,
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.rates = SNDRV_PCM_RATE_8000_48000,
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.formats = SNDRV_PCM_FMTBIT_S16_LE,
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},
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.ops = &max9867_dai_ops,
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.symmetric_rates = 1,
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@ -27,10 +27,8 @@
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#define MAX9867_PSCLK_20_40 0x2
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#define MAX9867_PSCLK_40_60 0x3
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#define MAX9867_AUDIOCLKHIGH 0x06
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#define MAX9867_NI_HIGH_WIDTH 0x7
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#define MAX9867_NI_HIGH_MASK 0x7F
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#define MAX9867_NI_LOW_MASK 0x7F
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#define MAX9867_NI_LOW_SHIFT 0x1
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#define MAX9867_NI_LOW_MASK 0xFE
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#define MAX9867_PLL (1<<7)
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#define MAX9867_AUDIOCLKLOW 0x07
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#define MAX9867_RAPID_LOCK 0x01
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@ -43,12 +41,12 @@
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#define MAX9867_BCI_MODE (1<<5)
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#define MAX9867_IFC1B 0x09
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#define MAX9867_IFC1B_BCLK_MASK 7
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#define MAX9867_IFC1B_32BIT 0x01
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#define MAX9867_IFC1B_24BIT 0x02
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#define MAX9867_IFC1B_PCLK_2 4
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#define MAX9867_IFC1B_PCLK_4 5
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#define MAX9867_IFC1B_PCLK_8 6
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#define MAX9867_IFC1B_PCLK_16 7
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#define MAX9867_IFC1B_64X 0x01
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#define MAX9867_IFC1B_48X 0x02
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#define MAX9867_IFC1B_PCLK_2 0x04
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#define MAX9867_IFC1B_PCLK_4 0x05
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#define MAX9867_IFC1B_PCLK_8 0x06
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#define MAX9867_IFC1B_PCLK_16 0x07
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#define MAX9867_CODECFLTR 0x0a
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#define MAX9867_DACGAIN 0x0b
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#define MAX9867_DACLEVEL 0x0c
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@ -72,11 +70,4 @@
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#define MAX9867_CACHEREGNUM 10
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/* codec private data */
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struct max9867_priv {
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struct regmap *regmap;
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unsigned int sysclk;
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unsigned int pclk;
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unsigned int master;
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};
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#endif
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