LoongArch: Add misc common routines
Add some misc common routines for LoongArch, including: asm-offsets routines, futex functions, i/o memory access functions, frame-buffer functions, procfs information display, etc. Reviewed-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
This commit is contained in:
Huacai Chen
parent
fcdfe9d22b
commit
7153c3cbb5
5
arch/loongarch/include/asm/asm-offsets.h
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5
arch/loongarch/include/asm/asm-offsets.h
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@ -0,0 +1,5 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
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*/
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#include <generated/asm-offsets.h>
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23
arch/loongarch/include/asm/fb.h
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23
arch/loongarch/include/asm/fb.h
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@ -0,0 +1,23 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
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*/
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#ifndef _ASM_FB_H_
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#define _ASM_FB_H_
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#include <linux/fb.h>
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#include <linux/fs.h>
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#include <asm/page.h>
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static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma,
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unsigned long off)
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{
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vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
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}
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static inline int fb_is_primary_device(struct fb_info *info)
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{
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return 0;
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}
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#endif /* _ASM_FB_H_ */
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107
arch/loongarch/include/asm/futex.h
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107
arch/loongarch/include/asm/futex.h
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@ -0,0 +1,107 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
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*/
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#ifndef _ASM_FUTEX_H
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#define _ASM_FUTEX_H
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#include <linux/futex.h>
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#include <linux/uaccess.h>
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#include <asm/barrier.h>
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#include <asm/compiler.h>
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#include <asm/errno.h>
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#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
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{ \
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__asm__ __volatile__( \
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"1: ll.w %1, %4 # __futex_atomic_op\n" \
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" " insn " \n" \
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"2: sc.w $t0, %2 \n" \
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" beq $t0, $zero, 1b \n" \
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"3: \n" \
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" .section .fixup,\"ax\" \n" \
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"4: li.w %0, %6 \n" \
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" b 3b \n" \
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" .previous \n" \
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" .section __ex_table,\"a\" \n" \
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" "__UA_ADDR "\t1b, 4b \n" \
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" "__UA_ADDR "\t2b, 4b \n" \
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" .previous \n" \
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: "=r" (ret), "=&r" (oldval), \
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"=ZC" (*uaddr) \
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: "0" (0), "ZC" (*uaddr), "Jr" (oparg), \
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"i" (-EFAULT) \
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: "memory", "t0"); \
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}
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static inline int
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arch_futex_atomic_op_inuser(int op, int oparg, int *oval, u32 __user *uaddr)
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{
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int oldval = 0, ret = 0;
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pagefault_disable();
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switch (op) {
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case FUTEX_OP_SET:
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__futex_atomic_op("move $t0, %z5", ret, oldval, uaddr, oparg);
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break;
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case FUTEX_OP_ADD:
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__futex_atomic_op("add.w $t0, %1, %z5", ret, oldval, uaddr, oparg);
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break;
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case FUTEX_OP_OR:
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__futex_atomic_op("or $t0, %1, %z5", ret, oldval, uaddr, oparg);
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break;
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case FUTEX_OP_ANDN:
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__futex_atomic_op("and $t0, %1, %z5", ret, oldval, uaddr, ~oparg);
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break;
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case FUTEX_OP_XOR:
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__futex_atomic_op("xor $t0, %1, %z5", ret, oldval, uaddr, oparg);
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break;
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default:
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ret = -ENOSYS;
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}
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pagefault_enable();
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if (!ret)
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*oval = oldval;
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return ret;
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}
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static inline int
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futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, u32 oldval, u32 newval)
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{
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int ret = 0;
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u32 val = 0;
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if (!access_ok(uaddr, sizeof(u32)))
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return -EFAULT;
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__asm__ __volatile__(
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"# futex_atomic_cmpxchg_inatomic \n"
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"1: ll.w %1, %3 \n"
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" bne %1, %z4, 3f \n"
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" or $t0, %z5, $zero \n"
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"2: sc.w $t0, %2 \n"
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" beq $zero, $t0, 1b \n"
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"3: \n"
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" .section .fixup,\"ax\" \n"
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"4: li.d %0, %6 \n"
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" b 3b \n"
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" .previous \n"
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" .section __ex_table,\"a\" \n"
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" "__UA_ADDR "\t1b, 4b \n"
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" "__UA_ADDR "\t2b, 4b \n"
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" .previous \n"
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: "+r" (ret), "=&r" (val), "=" GCC_OFF_SMALL_ASM() (*uaddr)
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: GCC_OFF_SMALL_ASM() (*uaddr), "Jr" (oldval), "Jr" (newval),
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"i" (-EFAULT)
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: "memory", "t0");
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*uval = val;
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return ret;
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}
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#endif /* _ASM_FUTEX_H */
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129
arch/loongarch/include/asm/io.h
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129
arch/loongarch/include/asm/io.h
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@ -0,0 +1,129 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
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*/
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#ifndef _ASM_IO_H
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#define _ASM_IO_H
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#define ARCH_HAS_IOREMAP_WC
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#include <linux/compiler.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <asm/addrspace.h>
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#include <asm/bug.h>
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#include <asm/byteorder.h>
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#include <asm/cpu.h>
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#include <asm/page.h>
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#include <asm/pgtable-bits.h>
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#include <asm/string.h>
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/*
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* On LoongArch, I/O ports mappring is following:
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*
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* | .... |
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* |-----------------------|
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* | pci io ports(64K~32M) |
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* |-----------------------|
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* | isa io ports(0 ~16K) |
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* PCI_IOBASE ->|-----------------------|
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* | .... |
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*/
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#define PCI_IOBASE ((void __iomem *)(vm_map_base + (2 * PAGE_SIZE)))
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#define PCI_IOSIZE SZ_32M
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#define ISA_IOSIZE SZ_16K
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#define IO_SPACE_LIMIT (PCI_IOSIZE - 1)
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/*
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* Change "struct page" to physical address.
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*/
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#define page_to_phys(page) ((phys_addr_t)page_to_pfn(page) << PAGE_SHIFT)
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extern void __init __iomem *early_ioremap(u64 phys_addr, unsigned long size);
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extern void __init early_iounmap(void __iomem *addr, unsigned long size);
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#define early_memremap early_ioremap
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#define early_memunmap early_iounmap
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static inline void __iomem *ioremap_prot(phys_addr_t offset, unsigned long size,
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unsigned long prot_val)
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{
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if (prot_val == _CACHE_CC)
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return (void __iomem *)(unsigned long)(CACHE_BASE + offset);
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else
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return (void __iomem *)(unsigned long)(UNCACHE_BASE + offset);
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}
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/*
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* ioremap - map bus memory into CPU space
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* @offset: bus address of the memory
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* @size: size of the resource to map
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*
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* ioremap performs a platform specific sequence of operations to
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* make bus memory CPU accessible via the readb/readw/readl/writeb/
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* writew/writel functions and the other mmio helpers. The returned
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* address is not guaranteed to be usable directly as a virtual
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* address.
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*/
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#define ioremap(offset, size) \
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ioremap_prot((offset), (size), _CACHE_SUC)
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/*
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* ioremap_wc - map bus memory into CPU space
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* @offset: bus address of the memory
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* @size: size of the resource to map
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*
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* ioremap_wc performs a platform specific sequence of operations to
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* make bus memory CPU accessible via the readb/readw/readl/writeb/
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* writew/writel functions and the other mmio helpers. The returned
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* address is not guaranteed to be usable directly as a virtual
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* address.
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*
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* This version of ioremap ensures that the memory is marked uncachable
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* but accelerated by means of write-combining feature. It is specifically
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* useful for PCIe prefetchable windows, which may vastly improve a
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* communications performance. If it was determined on boot stage, what
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* CPU CCA doesn't support WUC, the method shall fall-back to the
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* _CACHE_SUC option (see cpu_probe() method).
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*/
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#define ioremap_wc(offset, size) \
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ioremap_prot((offset), (size), _CACHE_WUC)
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/*
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* ioremap_cache - map bus memory into CPU space
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* @offset: bus address of the memory
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* @size: size of the resource to map
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*
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* ioremap_cache performs a platform specific sequence of operations to
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* make bus memory CPU accessible via the readb/readw/readl/writeb/
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* writew/writel functions and the other mmio helpers. The returned
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* address is not guaranteed to be usable directly as a virtual
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* address.
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*
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* This version of ioremap ensures that the memory is marked cachable by
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* the CPU. Also enables full write-combining. Useful for some
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* memory-like regions on I/O busses.
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*/
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#define ioremap_cache(offset, size) \
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ioremap_prot((offset), (size), _CACHE_CC)
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static inline void iounmap(const volatile void __iomem *addr)
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{
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}
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#define mmiowb() asm volatile ("dbar 0" ::: "memory")
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/*
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* String version of I/O memory access operations.
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*/
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extern void __memset_io(volatile void __iomem *dst, int c, size_t count);
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extern void __memcpy_toio(volatile void __iomem *to, const void *from, size_t count);
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extern void __memcpy_fromio(void *to, const volatile void __iomem *from, size_t count);
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#define memset_io(c, v, l) __memset_io((c), (v), (l))
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#define memcpy_fromio(a, c, l) __memcpy_fromio((a), (c), (l))
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#define memcpy_toio(c, a, l) __memcpy_toio((c), (a), (l))
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#include <asm-generic/io.h>
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#endif /* _ASM_IO_H */
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254
arch/loongarch/kernel/asm-offsets.c
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254
arch/loongarch/kernel/asm-offsets.c
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@ -0,0 +1,254 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* asm-offsets.c: Calculate pt_regs and task_struct offsets.
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*
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* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
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*/
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#include <linux/types.h>
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#include <linux/sched.h>
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#include <linux/mm.h>
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#include <linux/kbuild.h>
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#include <linux/suspend.h>
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#include <asm/cpu-info.h>
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#include <asm/ptrace.h>
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#include <asm/processor.h>
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void output_ptreg_defines(void)
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{
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COMMENT("LoongArch pt_regs offsets.");
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OFFSET(PT_R0, pt_regs, regs[0]);
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OFFSET(PT_R1, pt_regs, regs[1]);
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OFFSET(PT_R2, pt_regs, regs[2]);
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OFFSET(PT_R3, pt_regs, regs[3]);
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OFFSET(PT_R4, pt_regs, regs[4]);
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OFFSET(PT_R5, pt_regs, regs[5]);
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OFFSET(PT_R6, pt_regs, regs[6]);
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OFFSET(PT_R7, pt_regs, regs[7]);
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OFFSET(PT_R8, pt_regs, regs[8]);
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OFFSET(PT_R9, pt_regs, regs[9]);
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OFFSET(PT_R10, pt_regs, regs[10]);
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OFFSET(PT_R11, pt_regs, regs[11]);
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OFFSET(PT_R12, pt_regs, regs[12]);
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OFFSET(PT_R13, pt_regs, regs[13]);
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OFFSET(PT_R14, pt_regs, regs[14]);
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OFFSET(PT_R15, pt_regs, regs[15]);
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OFFSET(PT_R16, pt_regs, regs[16]);
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OFFSET(PT_R17, pt_regs, regs[17]);
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OFFSET(PT_R18, pt_regs, regs[18]);
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OFFSET(PT_R19, pt_regs, regs[19]);
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OFFSET(PT_R20, pt_regs, regs[20]);
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OFFSET(PT_R21, pt_regs, regs[21]);
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OFFSET(PT_R22, pt_regs, regs[22]);
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OFFSET(PT_R23, pt_regs, regs[23]);
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OFFSET(PT_R24, pt_regs, regs[24]);
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OFFSET(PT_R25, pt_regs, regs[25]);
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OFFSET(PT_R26, pt_regs, regs[26]);
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OFFSET(PT_R27, pt_regs, regs[27]);
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OFFSET(PT_R28, pt_regs, regs[28]);
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OFFSET(PT_R29, pt_regs, regs[29]);
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OFFSET(PT_R30, pt_regs, regs[30]);
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OFFSET(PT_R31, pt_regs, regs[31]);
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OFFSET(PT_CRMD, pt_regs, csr_crmd);
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OFFSET(PT_PRMD, pt_regs, csr_prmd);
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OFFSET(PT_EUEN, pt_regs, csr_euen);
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OFFSET(PT_ECFG, pt_regs, csr_ecfg);
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OFFSET(PT_ESTAT, pt_regs, csr_estat);
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OFFSET(PT_ERA, pt_regs, csr_era);
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OFFSET(PT_BVADDR, pt_regs, csr_badvaddr);
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OFFSET(PT_ORIG_A0, pt_regs, orig_a0);
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DEFINE(PT_SIZE, sizeof(struct pt_regs));
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BLANK();
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}
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void output_task_defines(void)
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{
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COMMENT("LoongArch task_struct offsets.");
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OFFSET(TASK_STATE, task_struct, __state);
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OFFSET(TASK_THREAD_INFO, task_struct, stack);
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OFFSET(TASK_FLAGS, task_struct, flags);
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OFFSET(TASK_MM, task_struct, mm);
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OFFSET(TASK_PID, task_struct, pid);
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DEFINE(TASK_STRUCT_SIZE, sizeof(struct task_struct));
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BLANK();
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}
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void output_thread_info_defines(void)
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{
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COMMENT("LoongArch thread_info offsets.");
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OFFSET(TI_TASK, thread_info, task);
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OFFSET(TI_FLAGS, thread_info, flags);
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OFFSET(TI_TP_VALUE, thread_info, tp_value);
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OFFSET(TI_CPU, thread_info, cpu);
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OFFSET(TI_PRE_COUNT, thread_info, preempt_count);
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OFFSET(TI_REGS, thread_info, regs);
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DEFINE(_THREAD_SIZE, THREAD_SIZE);
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DEFINE(_THREAD_MASK, THREAD_MASK);
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DEFINE(_IRQ_STACK_SIZE, IRQ_STACK_SIZE);
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DEFINE(_IRQ_STACK_START, IRQ_STACK_START);
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BLANK();
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}
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void output_thread_defines(void)
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{
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COMMENT("LoongArch specific thread_struct offsets.");
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OFFSET(THREAD_REG01, task_struct, thread.reg01);
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OFFSET(THREAD_REG03, task_struct, thread.reg03);
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OFFSET(THREAD_REG22, task_struct, thread.reg22);
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OFFSET(THREAD_REG23, task_struct, thread.reg23);
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OFFSET(THREAD_REG24, task_struct, thread.reg24);
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OFFSET(THREAD_REG25, task_struct, thread.reg25);
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OFFSET(THREAD_REG26, task_struct, thread.reg26);
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OFFSET(THREAD_REG27, task_struct, thread.reg27);
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OFFSET(THREAD_REG28, task_struct, thread.reg28);
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OFFSET(THREAD_REG29, task_struct, thread.reg29);
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OFFSET(THREAD_REG30, task_struct, thread.reg30);
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OFFSET(THREAD_REG31, task_struct, thread.reg31);
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OFFSET(THREAD_CSRCRMD, task_struct,
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thread.csr_crmd);
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OFFSET(THREAD_CSRPRMD, task_struct,
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thread.csr_prmd);
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OFFSET(THREAD_CSREUEN, task_struct,
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thread.csr_euen);
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OFFSET(THREAD_CSRECFG, task_struct,
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thread.csr_ecfg);
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OFFSET(THREAD_SCR0, task_struct, thread.scr0);
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OFFSET(THREAD_SCR1, task_struct, thread.scr1);
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OFFSET(THREAD_SCR2, task_struct, thread.scr2);
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OFFSET(THREAD_SCR3, task_struct, thread.scr3);
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OFFSET(THREAD_EFLAGS, task_struct, thread.eflags);
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OFFSET(THREAD_FPU, task_struct, thread.fpu);
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OFFSET(THREAD_BVADDR, task_struct, \
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thread.csr_badvaddr);
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OFFSET(THREAD_ECODE, task_struct, \
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thread.error_code);
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OFFSET(THREAD_TRAPNO, task_struct, thread.trap_nr);
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BLANK();
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}
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void output_thread_fpu_defines(void)
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{
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OFFSET(THREAD_FPR0, loongarch_fpu, fpr[0]);
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OFFSET(THREAD_FPR1, loongarch_fpu, fpr[1]);
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OFFSET(THREAD_FPR2, loongarch_fpu, fpr[2]);
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OFFSET(THREAD_FPR3, loongarch_fpu, fpr[3]);
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OFFSET(THREAD_FPR4, loongarch_fpu, fpr[4]);
|
||||
OFFSET(THREAD_FPR5, loongarch_fpu, fpr[5]);
|
||||
OFFSET(THREAD_FPR6, loongarch_fpu, fpr[6]);
|
||||
OFFSET(THREAD_FPR7, loongarch_fpu, fpr[7]);
|
||||
OFFSET(THREAD_FPR8, loongarch_fpu, fpr[8]);
|
||||
OFFSET(THREAD_FPR9, loongarch_fpu, fpr[9]);
|
||||
OFFSET(THREAD_FPR10, loongarch_fpu, fpr[10]);
|
||||
OFFSET(THREAD_FPR11, loongarch_fpu, fpr[11]);
|
||||
OFFSET(THREAD_FPR12, loongarch_fpu, fpr[12]);
|
||||
OFFSET(THREAD_FPR13, loongarch_fpu, fpr[13]);
|
||||
OFFSET(THREAD_FPR14, loongarch_fpu, fpr[14]);
|
||||
OFFSET(THREAD_FPR15, loongarch_fpu, fpr[15]);
|
||||
OFFSET(THREAD_FPR16, loongarch_fpu, fpr[16]);
|
||||
OFFSET(THREAD_FPR17, loongarch_fpu, fpr[17]);
|
||||
OFFSET(THREAD_FPR18, loongarch_fpu, fpr[18]);
|
||||
OFFSET(THREAD_FPR19, loongarch_fpu, fpr[19]);
|
||||
OFFSET(THREAD_FPR20, loongarch_fpu, fpr[20]);
|
||||
OFFSET(THREAD_FPR21, loongarch_fpu, fpr[21]);
|
||||
OFFSET(THREAD_FPR22, loongarch_fpu, fpr[22]);
|
||||
OFFSET(THREAD_FPR23, loongarch_fpu, fpr[23]);
|
||||
OFFSET(THREAD_FPR24, loongarch_fpu, fpr[24]);
|
||||
OFFSET(THREAD_FPR25, loongarch_fpu, fpr[25]);
|
||||
OFFSET(THREAD_FPR26, loongarch_fpu, fpr[26]);
|
||||
OFFSET(THREAD_FPR27, loongarch_fpu, fpr[27]);
|
||||
OFFSET(THREAD_FPR28, loongarch_fpu, fpr[28]);
|
||||
OFFSET(THREAD_FPR29, loongarch_fpu, fpr[29]);
|
||||
OFFSET(THREAD_FPR30, loongarch_fpu, fpr[30]);
|
||||
OFFSET(THREAD_FPR31, loongarch_fpu, fpr[31]);
|
||||
|
||||
OFFSET(THREAD_FCSR, loongarch_fpu, fcsr);
|
||||
OFFSET(THREAD_FCC, loongarch_fpu, fcc);
|
||||
OFFSET(THREAD_VCSR, loongarch_fpu, vcsr);
|
||||
BLANK();
|
||||
}
|
||||
|
||||
void output_mm_defines(void)
|
||||
{
|
||||
COMMENT("Size of struct page");
|
||||
DEFINE(STRUCT_PAGE_SIZE, sizeof(struct page));
|
||||
BLANK();
|
||||
COMMENT("Linux mm_struct offsets.");
|
||||
OFFSET(MM_USERS, mm_struct, mm_users);
|
||||
OFFSET(MM_PGD, mm_struct, pgd);
|
||||
OFFSET(MM_CONTEXT, mm_struct, context);
|
||||
BLANK();
|
||||
DEFINE(_PGD_T_SIZE, sizeof(pgd_t));
|
||||
DEFINE(_PMD_T_SIZE, sizeof(pmd_t));
|
||||
DEFINE(_PTE_T_SIZE, sizeof(pte_t));
|
||||
BLANK();
|
||||
DEFINE(_PGD_T_LOG2, PGD_T_LOG2);
|
||||
#ifndef __PAGETABLE_PMD_FOLDED
|
||||
DEFINE(_PMD_T_LOG2, PMD_T_LOG2);
|
||||
#endif
|
||||
DEFINE(_PTE_T_LOG2, PTE_T_LOG2);
|
||||
BLANK();
|
||||
DEFINE(_PGD_ORDER, PGD_ORDER);
|
||||
#ifndef __PAGETABLE_PMD_FOLDED
|
||||
DEFINE(_PMD_ORDER, PMD_ORDER);
|
||||
#endif
|
||||
DEFINE(_PTE_ORDER, PTE_ORDER);
|
||||
BLANK();
|
||||
DEFINE(_PMD_SHIFT, PMD_SHIFT);
|
||||
DEFINE(_PGDIR_SHIFT, PGDIR_SHIFT);
|
||||
BLANK();
|
||||
DEFINE(_PTRS_PER_PGD, PTRS_PER_PGD);
|
||||
DEFINE(_PTRS_PER_PMD, PTRS_PER_PMD);
|
||||
DEFINE(_PTRS_PER_PTE, PTRS_PER_PTE);
|
||||
BLANK();
|
||||
DEFINE(_PAGE_SHIFT, PAGE_SHIFT);
|
||||
DEFINE(_PAGE_SIZE, PAGE_SIZE);
|
||||
BLANK();
|
||||
}
|
||||
|
||||
void output_sc_defines(void)
|
||||
{
|
||||
COMMENT("Linux sigcontext offsets.");
|
||||
OFFSET(SC_REGS, sigcontext, sc_regs);
|
||||
OFFSET(SC_PC, sigcontext, sc_pc);
|
||||
BLANK();
|
||||
}
|
||||
|
||||
void output_signal_defines(void)
|
||||
{
|
||||
COMMENT("Linux signal numbers.");
|
||||
DEFINE(_SIGHUP, SIGHUP);
|
||||
DEFINE(_SIGINT, SIGINT);
|
||||
DEFINE(_SIGQUIT, SIGQUIT);
|
||||
DEFINE(_SIGILL, SIGILL);
|
||||
DEFINE(_SIGTRAP, SIGTRAP);
|
||||
DEFINE(_SIGIOT, SIGIOT);
|
||||
DEFINE(_SIGABRT, SIGABRT);
|
||||
DEFINE(_SIGFPE, SIGFPE);
|
||||
DEFINE(_SIGKILL, SIGKILL);
|
||||
DEFINE(_SIGBUS, SIGBUS);
|
||||
DEFINE(_SIGSEGV, SIGSEGV);
|
||||
DEFINE(_SIGSYS, SIGSYS);
|
||||
DEFINE(_SIGPIPE, SIGPIPE);
|
||||
DEFINE(_SIGALRM, SIGALRM);
|
||||
DEFINE(_SIGTERM, SIGTERM);
|
||||
DEFINE(_SIGUSR1, SIGUSR1);
|
||||
DEFINE(_SIGUSR2, SIGUSR2);
|
||||
DEFINE(_SIGCHLD, SIGCHLD);
|
||||
DEFINE(_SIGPWR, SIGPWR);
|
||||
DEFINE(_SIGWINCH, SIGWINCH);
|
||||
DEFINE(_SIGURG, SIGURG);
|
||||
DEFINE(_SIGIO, SIGIO);
|
||||
DEFINE(_SIGSTOP, SIGSTOP);
|
||||
DEFINE(_SIGTSTP, SIGTSTP);
|
||||
DEFINE(_SIGCONT, SIGCONT);
|
||||
DEFINE(_SIGTTIN, SIGTTIN);
|
||||
DEFINE(_SIGTTOU, SIGTTOU);
|
||||
DEFINE(_SIGVTALRM, SIGVTALRM);
|
||||
DEFINE(_SIGPROF, SIGPROF);
|
||||
DEFINE(_SIGXCPU, SIGXCPU);
|
||||
DEFINE(_SIGXFSZ, SIGXFSZ);
|
||||
BLANK();
|
||||
}
|
||||
94
arch/loongarch/kernel/io.c
Normal file
94
arch/loongarch/kernel/io.c
Normal file
@ -0,0 +1,94 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
|
||||
*/
|
||||
#include <linux/export.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
/*
|
||||
* Copy data from IO memory space to "real" memory space.
|
||||
*/
|
||||
void __memcpy_fromio(void *to, const volatile void __iomem *from, size_t count)
|
||||
{
|
||||
while (count && !IS_ALIGNED((unsigned long)from, 8)) {
|
||||
*(u8 *)to = __raw_readb(from);
|
||||
from++;
|
||||
to++;
|
||||
count--;
|
||||
}
|
||||
|
||||
while (count >= 8) {
|
||||
*(u64 *)to = __raw_readq(from);
|
||||
from += 8;
|
||||
to += 8;
|
||||
count -= 8;
|
||||
}
|
||||
|
||||
while (count) {
|
||||
*(u8 *)to = __raw_readb(from);
|
||||
from++;
|
||||
to++;
|
||||
count--;
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL(__memcpy_fromio);
|
||||
|
||||
/*
|
||||
* Copy data from "real" memory space to IO memory space.
|
||||
*/
|
||||
void __memcpy_toio(volatile void __iomem *to, const void *from, size_t count)
|
||||
{
|
||||
while (count && !IS_ALIGNED((unsigned long)to, 8)) {
|
||||
__raw_writeb(*(u8 *)from, to);
|
||||
from++;
|
||||
to++;
|
||||
count--;
|
||||
}
|
||||
|
||||
while (count >= 8) {
|
||||
__raw_writeq(*(u64 *)from, to);
|
||||
from += 8;
|
||||
to += 8;
|
||||
count -= 8;
|
||||
}
|
||||
|
||||
while (count) {
|
||||
__raw_writeb(*(u8 *)from, to);
|
||||
from++;
|
||||
to++;
|
||||
count--;
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL(__memcpy_toio);
|
||||
|
||||
/*
|
||||
* "memset" on IO memory space.
|
||||
*/
|
||||
void __memset_io(volatile void __iomem *dst, int c, size_t count)
|
||||
{
|
||||
u64 qc = (u8)c;
|
||||
|
||||
qc |= qc << 8;
|
||||
qc |= qc << 16;
|
||||
qc |= qc << 32;
|
||||
|
||||
while (count && !IS_ALIGNED((unsigned long)dst, 8)) {
|
||||
__raw_writeb(c, dst);
|
||||
dst++;
|
||||
count--;
|
||||
}
|
||||
|
||||
while (count >= 8) {
|
||||
__raw_writeq(qc, dst);
|
||||
dst += 8;
|
||||
count -= 8;
|
||||
}
|
||||
|
||||
while (count) {
|
||||
__raw_writeb(c, dst);
|
||||
dst++;
|
||||
count--;
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL(__memset_io);
|
||||
122
arch/loongarch/kernel/proc.c
Normal file
122
arch/loongarch/kernel/proc.c
Normal file
@ -0,0 +1,122 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
|
||||
*/
|
||||
#include <linux/delay.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/seq_file.h>
|
||||
#include <asm/bootinfo.h>
|
||||
#include <asm/cpu.h>
|
||||
#include <asm/cpu-features.h>
|
||||
#include <asm/idle.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/time.h>
|
||||
|
||||
/*
|
||||
* No lock; only written during early bootup by CPU 0.
|
||||
*/
|
||||
static RAW_NOTIFIER_HEAD(proc_cpuinfo_chain);
|
||||
|
||||
int __ref register_proc_cpuinfo_notifier(struct notifier_block *nb)
|
||||
{
|
||||
return raw_notifier_chain_register(&proc_cpuinfo_chain, nb);
|
||||
}
|
||||
|
||||
int proc_cpuinfo_notifier_call_chain(unsigned long val, void *v)
|
||||
{
|
||||
return raw_notifier_call_chain(&proc_cpuinfo_chain, val, v);
|
||||
}
|
||||
|
||||
static int show_cpuinfo(struct seq_file *m, void *v)
|
||||
{
|
||||
unsigned long n = (unsigned long) v - 1;
|
||||
unsigned int version = cpu_data[n].processor_id & 0xff;
|
||||
unsigned int fp_version = cpu_data[n].fpu_vers;
|
||||
struct proc_cpuinfo_notifier_args proc_cpuinfo_notifier_args;
|
||||
|
||||
/*
|
||||
* For the first processor also print the system type
|
||||
*/
|
||||
if (n == 0)
|
||||
seq_printf(m, "system type\t\t: %s\n\n", get_system_type());
|
||||
|
||||
seq_printf(m, "processor\t\t: %ld\n", n);
|
||||
seq_printf(m, "package\t\t\t: %d\n", cpu_data[n].package);
|
||||
seq_printf(m, "core\t\t\t: %d\n", cpu_data[n].core);
|
||||
seq_printf(m, "CPU Family\t\t: %s\n", __cpu_family[n]);
|
||||
seq_printf(m, "Model Name\t\t: %s\n", __cpu_full_name[n]);
|
||||
seq_printf(m, "CPU Revision\t\t: 0x%02x\n", version);
|
||||
seq_printf(m, "FPU Revision\t\t: 0x%02x\n", fp_version);
|
||||
seq_printf(m, "CPU MHz\t\t\t: %llu.%02llu\n",
|
||||
cpu_clock_freq / 1000000, (cpu_clock_freq / 10000) % 100);
|
||||
seq_printf(m, "BogoMIPS\t\t: %llu.%02llu\n",
|
||||
(lpj_fine * cpu_clock_freq / const_clock_freq) / (500000/HZ),
|
||||
((lpj_fine * cpu_clock_freq / const_clock_freq) / (5000/HZ)) % 100);
|
||||
seq_printf(m, "TLB Entries\t\t: %d\n", cpu_data[n].tlbsize);
|
||||
seq_printf(m, "Address Sizes\t\t: %d bits physical, %d bits virtual\n",
|
||||
cpu_pabits + 1, cpu_vabits + 1);
|
||||
|
||||
seq_printf(m, "ISA\t\t\t:");
|
||||
if (cpu_has_loongarch32)
|
||||
seq_printf(m, " loongarch32");
|
||||
if (cpu_has_loongarch64)
|
||||
seq_printf(m, " loongarch64");
|
||||
seq_printf(m, "\n");
|
||||
|
||||
seq_printf(m, "Features\t\t:");
|
||||
if (cpu_has_cpucfg) seq_printf(m, " cpucfg");
|
||||
if (cpu_has_lam) seq_printf(m, " lam");
|
||||
if (cpu_has_ual) seq_printf(m, " ual");
|
||||
if (cpu_has_fpu) seq_printf(m, " fpu");
|
||||
if (cpu_has_lsx) seq_printf(m, " lsx");
|
||||
if (cpu_has_lasx) seq_printf(m, " lasx");
|
||||
if (cpu_has_complex) seq_printf(m, " complex");
|
||||
if (cpu_has_crypto) seq_printf(m, " crypto");
|
||||
if (cpu_has_lvz) seq_printf(m, " lvz");
|
||||
if (cpu_has_lbt_x86) seq_printf(m, " lbt_x86");
|
||||
if (cpu_has_lbt_arm) seq_printf(m, " lbt_arm");
|
||||
if (cpu_has_lbt_mips) seq_printf(m, " lbt_mips");
|
||||
seq_printf(m, "\n");
|
||||
|
||||
seq_printf(m, "Hardware Watchpoint\t: %s",
|
||||
cpu_has_watch ? "yes, " : "no\n");
|
||||
if (cpu_has_watch) {
|
||||
seq_printf(m, "iwatch count: %d, dwatch count: %d\n",
|
||||
cpu_data[n].watch_ireg_count, cpu_data[n].watch_dreg_count);
|
||||
}
|
||||
|
||||
proc_cpuinfo_notifier_args.m = m;
|
||||
proc_cpuinfo_notifier_args.n = n;
|
||||
|
||||
raw_notifier_call_chain(&proc_cpuinfo_chain, 0,
|
||||
&proc_cpuinfo_notifier_args);
|
||||
|
||||
seq_printf(m, "\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void *c_start(struct seq_file *m, loff_t *pos)
|
||||
{
|
||||
unsigned long i = *pos;
|
||||
|
||||
return i < NR_CPUS ? (void *)(i + 1) : NULL;
|
||||
}
|
||||
|
||||
static void *c_next(struct seq_file *m, void *v, loff_t *pos)
|
||||
{
|
||||
++*pos;
|
||||
return c_start(m, pos);
|
||||
}
|
||||
|
||||
static void c_stop(struct seq_file *m, void *v)
|
||||
{
|
||||
}
|
||||
|
||||
const struct seq_operations cpuinfo_op = {
|
||||
.start = c_start,
|
||||
.next = c_next,
|
||||
.stop = c_stop,
|
||||
.show = show_cpuinfo,
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user