mlxsw: reg: Add Tunneling NVE General Configuration Register
This register configures global NVE configuration such as source IP of the NVE tunnel and UDP source port calculation. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Reviewed-by: Petr Machata <petrm@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Ido Schimmel
David S. Miller
parent
beda7f72c3
commit
710dd1a0ec
@ -8292,6 +8292,190 @@ static inline void mlxsw_reg_mgpc_pack(char *payload, u32 counter_index,
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mlxsw_reg_mgpc_opcode_set(payload, opcode);
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}
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/* TNGCR - Tunneling NVE General Configuration Register
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* ----------------------------------------------------
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* The TNGCR register is used for setting up the NVE Tunneling configuration.
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*/
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#define MLXSW_REG_TNGCR_ID 0xA001
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#define MLXSW_REG_TNGCR_LEN 0x44
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MLXSW_REG_DEFINE(tngcr, MLXSW_REG_TNGCR_ID, MLXSW_REG_TNGCR_LEN);
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enum mlxsw_reg_tngcr_type {
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MLXSW_REG_TNGCR_TYPE_VXLAN,
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MLXSW_REG_TNGCR_TYPE_VXLAN_GPE,
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MLXSW_REG_TNGCR_TYPE_GENEVE,
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MLXSW_REG_TNGCR_TYPE_NVGRE,
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};
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/* reg_tngcr_type
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* Tunnel type for encapsulation and decapsulation. The types are mutually
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* exclusive.
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* Note: For Spectrum the NVE parsing must be enabled in MPRS.
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* Access: RW
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*/
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MLXSW_ITEM32(reg, tngcr, type, 0x00, 0, 4);
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/* reg_tngcr_nve_valid
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* The VTEP is valid. Allows adding FDB entries for tunnel encapsulation.
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* Access: RW
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*/
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MLXSW_ITEM32(reg, tngcr, nve_valid, 0x04, 31, 1);
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/* reg_tngcr_nve_ttl_uc
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* The TTL for NVE tunnel encapsulation underlay unicast packets.
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* Access: RW
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*/
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MLXSW_ITEM32(reg, tngcr, nve_ttl_uc, 0x04, 0, 8);
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/* reg_tngcr_nve_ttl_mc
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* The TTL for NVE tunnel encapsulation underlay multicast packets.
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* Access: RW
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*/
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MLXSW_ITEM32(reg, tngcr, nve_ttl_mc, 0x08, 0, 8);
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enum {
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/* Do not copy flow label. Calculate flow label using nve_flh. */
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MLXSW_REG_TNGCR_FL_NO_COPY,
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/* Copy flow label from inner packet if packet is IPv6 and
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* encapsulation is by IPv6. Otherwise, calculate flow label using
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* nve_flh.
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*/
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MLXSW_REG_TNGCR_FL_COPY,
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};
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/* reg_tngcr_nve_flc
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* For NVE tunnel encapsulation: Flow label copy from inner packet.
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* Access: RW
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*/
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MLXSW_ITEM32(reg, tngcr, nve_flc, 0x0C, 25, 1);
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enum {
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/* Flow label is static. In Spectrum this means '0'. Spectrum-2
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* uses {nve_fl_prefix, nve_fl_suffix}.
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*/
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MLXSW_REG_TNGCR_FL_NO_HASH,
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/* 8 LSBs of the flow label are calculated from ECMP hash of the
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* inner packet. 12 MSBs are configured by nve_fl_prefix.
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*/
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MLXSW_REG_TNGCR_FL_HASH,
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};
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/* reg_tngcr_nve_flh
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* NVE flow label hash.
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* Access: RW
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*/
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MLXSW_ITEM32(reg, tngcr, nve_flh, 0x0C, 24, 1);
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/* reg_tngcr_nve_fl_prefix
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* NVE flow label prefix. Constant 12 MSBs of the flow label.
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* Access: RW
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*/
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MLXSW_ITEM32(reg, tngcr, nve_fl_prefix, 0x0C, 8, 12);
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/* reg_tngcr_nve_fl_suffix
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* NVE flow label suffix. Constant 8 LSBs of the flow label.
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* Reserved when nve_flh=1 and for Spectrum.
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* Access: RW
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*/
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MLXSW_ITEM32(reg, tngcr, nve_fl_suffix, 0x0C, 0, 8);
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enum {
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/* Source UDP port is fixed (default '0') */
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MLXSW_REG_TNGCR_UDP_SPORT_NO_HASH,
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/* Source UDP port is calculated based on hash */
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MLXSW_REG_TNGCR_UDP_SPORT_HASH,
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};
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/* reg_tngcr_nve_udp_sport_type
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* NVE UDP source port type.
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* Spectrum uses LAG hash (SLCRv2). Spectrum-2 uses ECMP hash (RECRv2).
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* When the source UDP port is calculated based on hash, then the 8 LSBs
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* are calculated from hash the 8 MSBs are configured by
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* nve_udp_sport_prefix.
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* Access: RW
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*/
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MLXSW_ITEM32(reg, tngcr, nve_udp_sport_type, 0x10, 24, 1);
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/* reg_tngcr_nve_udp_sport_prefix
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* NVE UDP source port prefix. Constant 8 MSBs of the UDP source port.
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* Reserved when NVE type is NVGRE.
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* Access: RW
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*/
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MLXSW_ITEM32(reg, tngcr, nve_udp_sport_prefix, 0x10, 8, 8);
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/* reg_tngcr_nve_group_size_mc
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* The amount of sequential linked lists of MC entries. The first linked
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* list is configured by SFD.underlay_mc_ptr.
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* Valid values: 1, 2, 4, 8, 16, 32, 64
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* The linked list are configured by TNUMT.
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* The hash is set by LAG hash.
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* Access: RW
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*/
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MLXSW_ITEM32(reg, tngcr, nve_group_size_mc, 0x18, 0, 8);
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/* reg_tngcr_nve_group_size_flood
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* The amount of sequential linked lists of flooding entries. The first
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* linked list is configured by SFMR.nve_tunnel_flood_ptr
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* Valid values: 1, 2, 4, 8, 16, 32, 64
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* The linked list are configured by TNUMT.
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* The hash is set by LAG hash.
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* Access: RW
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*/
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MLXSW_ITEM32(reg, tngcr, nve_group_size_flood, 0x1C, 0, 8);
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/* reg_tngcr_learn_enable
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* During decapsulation, whether to learn from NVE port.
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* Reserved when Spectrum-2. See TNPC.
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* Access: RW
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*/
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MLXSW_ITEM32(reg, tngcr, learn_enable, 0x20, 31, 1);
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/* reg_tngcr_underlay_virtual_router
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* Underlay virtual router.
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* Reserved when Spectrum-2.
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* Access: RW
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*/
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MLXSW_ITEM32(reg, tngcr, underlay_virtual_router, 0x20, 0, 16);
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/* reg_tngcr_underlay_rif
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* Underlay ingress router interface. RIF type should be loopback generic.
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* Reserved when Spectrum.
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* Access: RW
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*/
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MLXSW_ITEM32(reg, tngcr, underlay_rif, 0x24, 0, 16);
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/* reg_tngcr_usipv4
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* Underlay source IPv4 address of the NVE.
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* Access: RW
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*/
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MLXSW_ITEM32(reg, tngcr, usipv4, 0x28, 0, 32);
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/* reg_tngcr_usipv6
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* Underlay source IPv6 address of the NVE. For Spectrum, must not be
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* modified under traffic of NVE tunneling encapsulation.
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* Access: RW
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*/
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MLXSW_ITEM_BUF(reg, tngcr, usipv6, 0x30, 16);
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static inline void mlxsw_reg_tngcr_pack(char *payload,
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enum mlxsw_reg_tngcr_type type,
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bool valid, u8 ttl)
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{
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MLXSW_REG_ZERO(tngcr, payload);
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mlxsw_reg_tngcr_type_set(payload, type);
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mlxsw_reg_tngcr_nve_valid_set(payload, valid);
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mlxsw_reg_tngcr_nve_ttl_uc_set(payload, ttl);
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mlxsw_reg_tngcr_nve_ttl_mc_set(payload, ttl);
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mlxsw_reg_tngcr_nve_flc_set(payload, MLXSW_REG_TNGCR_FL_NO_COPY);
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mlxsw_reg_tngcr_nve_flh_set(payload, 0);
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mlxsw_reg_tngcr_nve_udp_sport_type_set(payload,
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MLXSW_REG_TNGCR_UDP_SPORT_HASH);
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mlxsw_reg_tngcr_nve_udp_sport_prefix_set(payload, 0);
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mlxsw_reg_tngcr_nve_group_size_mc_set(payload, 1);
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mlxsw_reg_tngcr_nve_group_size_flood_set(payload, 1);
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}
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/* TIGCR - Tunneling IPinIP General Configuration Register
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* -------------------------------------------------------
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* The TIGCR register is used for setting up the IPinIP Tunnel configuration.
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@ -8841,6 +9025,7 @@ static const struct mlxsw_reg_info *mlxsw_reg_infos[] = {
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MLXSW_REG(mcc),
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MLXSW_REG(mcda),
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MLXSW_REG(mgpc),
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MLXSW_REG(tngcr),
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MLXSW_REG(tigcr),
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MLXSW_REG(sbpr),
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MLXSW_REG(sbcm),
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