forked from Minki/linux
iwlwifi: move 3945 SCD registers to iwl-prph.h
This patch moves 3945 SCD registers to iwl-prph.h. These registers are assigned from the periphery bus Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com> Signed-off-by: Tomas Winkler <tomas.winkler@intel.com> Signed-off-by: Zhu Yi <yi.zhu@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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67dc320d47
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7088310908
@ -805,18 +805,18 @@ static int iwl3945_tx_reset(struct iwl_priv *priv)
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}
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}
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/* bypass mode */
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/* bypass mode */
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iwl_write_prph(priv, SCD_MODE_REG, 0x2);
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iwl_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
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/* RA 0 is active */
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/* RA 0 is active */
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iwl_write_prph(priv, SCD_ARASTAT_REG, 0x01);
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iwl_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
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/* all 6 fifo are active */
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/* all 6 fifo are active */
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iwl_write_prph(priv, SCD_TXFACT_REG, 0x3f);
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iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
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iwl_write_prph(priv, SCD_SBYP_MODE_1_REG, 0x010000);
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iwl_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
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iwl_write_prph(priv, SCD_SBYP_MODE_2_REG, 0x030002);
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iwl_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
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iwl_write_prph(priv, SCD_TXF4MF_REG, 0x000004);
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iwl_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
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iwl_write_prph(priv, SCD_TXF5MF_REG, 0x000005);
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iwl_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
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iwl_write_direct32(priv, FH_TSSR_CBB_BASE,
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iwl_write_direct32(priv, FH_TSSR_CBB_BASE,
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priv->hw_setting.shared_phys);
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priv->hw_setting.shared_phys);
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@ -1044,7 +1044,7 @@ void iwl_hw_txq_ctx_stop(struct iwl_priv *priv)
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}
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}
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/* stop SCD */
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/* stop SCD */
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iwl_write_prph(priv, SCD_MODE_REG, 0);
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iwl_write_prph(priv, ALM_SCD_MODE_REG, 0);
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/* reset TFD queues */
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/* reset TFD queues */
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for (queue = TFD_QUEUE_MIN; queue < TFD_QUEUE_MAX; queue++) {
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for (queue = TFD_QUEUE_MIN; queue < TFD_QUEUE_MAX; queue++) {
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@ -225,6 +225,18 @@
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#define BSM_SRAM_LOWER_BOUND (PRPH_BASE + 0x3800)
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#define BSM_SRAM_LOWER_BOUND (PRPH_BASE + 0x3800)
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#define BSM_SRAM_SIZE (1024) /* bytes */
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#define BSM_SRAM_SIZE (1024) /* bytes */
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/* ALM SCD */
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/* SCD (Scheduler) */
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#define ALM_SCD_BASE (PRPH_BASE + 0x2E00)
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#define ALM_SCD_MODE_REG (ALM_SCD_BASE + 0x000)
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#define ALM_SCD_ARASTAT_REG (ALM_SCD_BASE + 0x004)
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#define ALM_SCD_TXFACT_REG (ALM_SCD_BASE + 0x010)
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#define ALM_SCD_TXF4MF_REG (ALM_SCD_BASE + 0x014)
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#define ALM_SCD_TXF5MF_REG (ALM_SCD_BASE + 0x020)
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#define ALM_SCD_SBYP_MODE_1_REG (ALM_SCD_BASE + 0x02C)
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#define ALM_SCD_SBYP_MODE_2_REG (ALM_SCD_BASE + 0x030)
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/* 4965 SCD memory mapped registers */
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/* 4965 SCD memory mapped registers */
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#define KDR_SCD_BASE (PRPH_BASE + 0xa02c00)
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#define KDR_SCD_BASE (PRPH_BASE + 0xa02c00)
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