rtlwifi: rtl8192se: Merge firmware routines
Merge routines fw.c and fw.h for RTL8192SE. In addition, make changes to rtlwifi/wifi.h to support RTL8192SE. Signed-off-by: Chaoming_Li <chaoming_li@realsil.com.cn> Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Chaoming Li
John W. Linville
parent
9fe255ee3c
commit
701307a885
654
drivers/net/wireless/rtlwifi/rtl8192se/fw.c
Normal file
654
drivers/net/wireless/rtlwifi/rtl8192se/fw.c
Normal file
@ -0,0 +1,654 @@
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/******************************************************************************
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*
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* Copyright(c) 2009-2010 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#include "../wifi.h"
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#include "../pci.h"
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#include "../base.h"
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#include "reg.h"
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#include "def.h"
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#include "fw.h"
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static void _rtl92s_fw_set_rqpn(struct ieee80211_hw *hw)
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{
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struct rtl_priv *rtlpriv = rtl_priv(hw);
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rtl_write_dword(rtlpriv, RQPN, 0xffffffff);
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rtl_write_dword(rtlpriv, RQPN + 4, 0xffffffff);
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rtl_write_byte(rtlpriv, RQPN + 8, 0xff);
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rtl_write_byte(rtlpriv, RQPN + 0xB, 0x80);
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}
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static bool _rtl92s_firmware_enable_cpu(struct ieee80211_hw *hw)
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{
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struct rtl_priv *rtlpriv = rtl_priv(hw);
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u32 ichecktime = 200;
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u16 tmpu2b;
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u8 tmpu1b, cpustatus = 0;
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_rtl92s_fw_set_rqpn(hw);
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/* Enable CPU. */
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tmpu1b = rtl_read_byte(rtlpriv, SYS_CLKR);
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/* AFE source */
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rtl_write_byte(rtlpriv, SYS_CLKR, (tmpu1b | SYS_CPU_CLKSEL));
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tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
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rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | FEN_CPUEN));
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/* Polling IMEM Ready after CPU has refilled. */
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do {
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cpustatus = rtl_read_byte(rtlpriv, TCR);
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if (cpustatus & IMEM_RDY) {
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RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
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("IMEM Ready after CPU has refilled.\n"));
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break;
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}
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udelay(100);
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} while (ichecktime--);
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if (!(cpustatus & IMEM_RDY))
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return false;
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return true;
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}
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static enum fw_status _rtl92s_firmware_get_nextstatus(
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enum fw_status fw_currentstatus)
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{
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enum fw_status next_fwstatus = 0;
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switch (fw_currentstatus) {
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case FW_STATUS_INIT:
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next_fwstatus = FW_STATUS_LOAD_IMEM;
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break;
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case FW_STATUS_LOAD_IMEM:
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next_fwstatus = FW_STATUS_LOAD_EMEM;
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break;
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case FW_STATUS_LOAD_EMEM:
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next_fwstatus = FW_STATUS_LOAD_DMEM;
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break;
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case FW_STATUS_LOAD_DMEM:
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next_fwstatus = FW_STATUS_READY;
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break;
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default:
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break;
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}
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return next_fwstatus;
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}
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static u8 _rtl92s_firmware_header_map_rftype(struct ieee80211_hw *hw)
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{
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struct rtl_priv *rtlpriv = rtl_priv(hw);
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struct rtl_phy *rtlphy = &(rtlpriv->phy);
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switch (rtlphy->rf_type) {
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case RF_1T1R:
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return 0x11;
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break;
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case RF_1T2R:
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return 0x12;
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break;
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case RF_2T2R:
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return 0x22;
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break;
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default:
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RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
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("Unknown RF type(%x)\n",
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rtlphy->rf_type));
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break;
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}
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return 0x22;
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}
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static void _rtl92s_firmwareheader_priveupdate(struct ieee80211_hw *hw,
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struct fw_priv *pfw_priv)
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{
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/* Update RF types for RATR settings. */
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pfw_priv->rf_config = _rtl92s_firmware_header_map_rftype(hw);
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}
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static bool _rtl92s_cmd_send_packet(struct ieee80211_hw *hw,
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struct sk_buff *skb, u8 last)
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{
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struct rtl_priv *rtlpriv = rtl_priv(hw);
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struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
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struct rtl8192_tx_ring *ring;
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struct rtl_tx_desc *pdesc;
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unsigned long flags;
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u8 idx = 0;
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ring = &rtlpci->tx_ring[TXCMD_QUEUE];
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spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
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idx = (ring->idx + skb_queue_len(&ring->queue)) % ring->entries;
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pdesc = &ring->desc[idx];
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rtlpriv->cfg->ops->fill_tx_cmddesc(hw, (u8 *)pdesc, 1, 1, skb);
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__skb_queue_tail(&ring->queue, skb);
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spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
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return true;
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}
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static bool _rtl92s_firmware_downloadcode(struct ieee80211_hw *hw,
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u8 *code_virtual_address, u32 buffer_len)
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{
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struct rtl_priv *rtlpriv = rtl_priv(hw);
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struct sk_buff *skb;
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struct rtl_tcb_desc *tcb_desc;
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unsigned char *seg_ptr;
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u16 frag_threshold = MAX_FIRMWARE_CODE_SIZE;
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u16 frag_length, frag_offset = 0;
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u16 extra_descoffset = 0;
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u8 last_inipkt = 0;
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_rtl92s_fw_set_rqpn(hw);
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if (buffer_len >= MAX_FIRMWARE_CODE_SIZE) {
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RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
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("Size over FIRMWARE_CODE_SIZE!\n"));
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return false;
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}
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extra_descoffset = 0;
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do {
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if ((buffer_len - frag_offset) > frag_threshold) {
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frag_length = frag_threshold + extra_descoffset;
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} else {
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frag_length = (u16)(buffer_len - frag_offset +
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extra_descoffset);
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last_inipkt = 1;
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}
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/* Allocate skb buffer to contain firmware */
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/* info and tx descriptor info. */
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skb = dev_alloc_skb(frag_length);
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skb_reserve(skb, extra_descoffset);
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seg_ptr = (u8 *)skb_put(skb, (u32)(frag_length -
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extra_descoffset));
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memcpy(seg_ptr, code_virtual_address + frag_offset,
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(u32)(frag_length - extra_descoffset));
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tcb_desc = (struct rtl_tcb_desc *)(skb->cb);
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tcb_desc->queue_index = TXCMD_QUEUE;
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tcb_desc->cmd_or_init = DESC_PACKET_TYPE_INIT;
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tcb_desc->last_inipkt = last_inipkt;
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_rtl92s_cmd_send_packet(hw, skb, last_inipkt);
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frag_offset += (frag_length - extra_descoffset);
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} while (frag_offset < buffer_len);
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rtl_write_byte(rtlpriv, TP_POLL, TPPOLL_CQ);
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return true ;
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}
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static bool _rtl92s_firmware_checkready(struct ieee80211_hw *hw,
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u8 loadfw_status)
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{
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struct rtl_priv *rtlpriv = rtl_priv(hw);
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struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
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struct rt_firmware *firmware = (struct rt_firmware *)rtlhal->pfirmware;
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u32 tmpu4b;
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u8 cpustatus = 0;
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short pollingcnt = 1000;
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bool rtstatus = true;
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RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("LoadStaus(%d)\n",
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loadfw_status));
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firmware->fwstatus = (enum fw_status)loadfw_status;
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switch (loadfw_status) {
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case FW_STATUS_LOAD_IMEM:
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/* Polling IMEM code done. */
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do {
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cpustatus = rtl_read_byte(rtlpriv, TCR);
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if (cpustatus & IMEM_CODE_DONE)
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break;
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udelay(5);
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} while (pollingcnt--);
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if (!(cpustatus & IMEM_CHK_RPT) || (pollingcnt <= 0)) {
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RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
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("FW_STATUS_LOAD_IMEM"
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" FAIL CPU, Status=%x\r\n", cpustatus));
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goto status_check_fail;
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}
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break;
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case FW_STATUS_LOAD_EMEM:
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/* Check Put Code OK and Turn On CPU */
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/* Polling EMEM code done. */
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do {
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cpustatus = rtl_read_byte(rtlpriv, TCR);
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if (cpustatus & EMEM_CODE_DONE)
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break;
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udelay(5);
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} while (pollingcnt--);
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if (!(cpustatus & EMEM_CHK_RPT) || (pollingcnt <= 0)) {
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RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
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("FW_STATUS_LOAD_EMEM"
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" FAIL CPU, Status=%x\r\n", cpustatus));
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goto status_check_fail;
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}
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/* Turn On CPU */
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rtstatus = _rtl92s_firmware_enable_cpu(hw);
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if (rtstatus != true) {
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RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
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("Enable CPU fail!\n"));
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goto status_check_fail;
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}
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break;
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case FW_STATUS_LOAD_DMEM:
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/* Polling DMEM code done */
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do {
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cpustatus = rtl_read_byte(rtlpriv, TCR);
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if (cpustatus & DMEM_CODE_DONE)
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break;
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udelay(5);
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} while (pollingcnt--);
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if (!(cpustatus & DMEM_CODE_DONE) || (pollingcnt <= 0)) {
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RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
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("Polling DMEM code done"
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" fail ! cpustatus(%#x)\n", cpustatus));
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goto status_check_fail;
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}
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RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
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("DMEM code download success,"
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" cpustatus(%#x)\n", cpustatus));
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/* Prevent Delay too much and being scheduled out */
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/* Polling Load Firmware ready */
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pollingcnt = 2000;
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do {
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cpustatus = rtl_read_byte(rtlpriv, TCR);
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if (cpustatus & FWRDY)
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break;
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udelay(40);
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} while (pollingcnt--);
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RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
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("Polling Load Firmware ready,"
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" cpustatus(%x)\n", cpustatus));
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if (((cpustatus & LOAD_FW_READY) != LOAD_FW_READY) ||
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(pollingcnt <= 0)) {
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RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
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("Polling Load Firmware"
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" ready fail ! cpustatus(%x)\n", cpustatus));
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goto status_check_fail;
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}
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/* If right here, we can set TCR/RCR to desired value */
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/* and config MAC lookback mode to normal mode */
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tmpu4b = rtl_read_dword(rtlpriv, TCR);
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rtl_write_dword(rtlpriv, TCR, (tmpu4b & (~TCR_ICV)));
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tmpu4b = rtl_read_dword(rtlpriv, RCR);
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rtl_write_dword(rtlpriv, RCR, (tmpu4b | RCR_APPFCS |
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RCR_APP_ICV | RCR_APP_MIC));
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RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
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("Current RCR settings(%#x)\n", tmpu4b));
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/* Set to normal mode. */
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rtl_write_byte(rtlpriv, LBKMD_SEL, LBK_NORMAL);
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break;
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default:
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RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
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("Unknown status check!\n"));
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rtstatus = false;
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break;
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}
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status_check_fail:
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RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("loadfw_status(%d), "
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"rtstatus(%x)\n", loadfw_status, rtstatus));
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return rtstatus;
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}
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int rtl92s_download_fw(struct ieee80211_hw *hw)
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{
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struct rtl_priv *rtlpriv = rtl_priv(hw);
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struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
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struct rt_firmware *firmware = NULL;
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struct fw_hdr *pfwheader;
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struct fw_priv *pfw_priv = NULL;
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u8 *puc_mappedfile = NULL;
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u32 ul_filelength = 0;
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u32 file_length = 0;
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u8 fwhdr_size = RT_8192S_FIRMWARE_HDR_SIZE;
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u8 fwstatus = FW_STATUS_INIT;
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bool rtstatus = true;
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if (!rtlhal->pfirmware)
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return 1;
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firmware = (struct rt_firmware *)rtlhal->pfirmware;
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firmware->fwstatus = FW_STATUS_INIT;
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puc_mappedfile = firmware->sz_fw_tmpbuffer;
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file_length = firmware->sz_fw_tmpbufferlen;
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/* 1. Retrieve FW header. */
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firmware->pfwheader = (struct fw_hdr *) puc_mappedfile;
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pfwheader = firmware->pfwheader;
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firmware->firmwareversion = byte(pfwheader->version, 0);
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firmware->pfwheader->fwpriv.hci_sel = 1;/* pcie */
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RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("signature:%x, version:"
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"%x, size:%x,"
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"imemsize:%x, sram size:%x\n", pfwheader->signature,
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pfwheader->version, pfwheader->dmem_size,
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pfwheader->img_imem_size, pfwheader->img_sram_size));
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/* 2. Retrieve IMEM image. */
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if ((pfwheader->img_imem_size == 0) || (pfwheader->img_imem_size >
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sizeof(firmware->fw_imem))) {
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RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
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("memory for data image is less than IMEM required\n"));
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goto fail;
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} else {
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puc_mappedfile += fwhdr_size;
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memcpy(firmware->fw_imem, puc_mappedfile,
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pfwheader->img_imem_size);
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firmware->fw_imem_len = pfwheader->img_imem_size;
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}
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/* 3. Retriecve EMEM image. */
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if (pfwheader->img_sram_size > sizeof(firmware->fw_emem)) {
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RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
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("memory for data image is less than EMEM required\n"));
|
||||
goto fail;
|
||||
} else {
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puc_mappedfile += firmware->fw_imem_len;
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memcpy(firmware->fw_emem, puc_mappedfile,
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pfwheader->img_sram_size);
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firmware->fw_emem_len = pfwheader->img_sram_size;
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}
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/* 4. download fw now */
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fwstatus = _rtl92s_firmware_get_nextstatus(firmware->fwstatus);
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while (fwstatus != FW_STATUS_READY) {
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/* Image buffer redirection. */
|
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switch (fwstatus) {
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case FW_STATUS_LOAD_IMEM:
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puc_mappedfile = firmware->fw_imem;
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ul_filelength = firmware->fw_imem_len;
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break;
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case FW_STATUS_LOAD_EMEM:
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puc_mappedfile = firmware->fw_emem;
|
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ul_filelength = firmware->fw_emem_len;
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break;
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||||
case FW_STATUS_LOAD_DMEM:
|
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/* Partial update the content of header private. */
|
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pfwheader = firmware->pfwheader;
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pfw_priv = &pfwheader->fwpriv;
|
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_rtl92s_firmwareheader_priveupdate(hw, pfw_priv);
|
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puc_mappedfile = (u8 *)(firmware->pfwheader) +
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RT_8192S_FIRMWARE_HDR_EXCLUDE_PRI_SIZE;
|
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ul_filelength = fwhdr_size -
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||||
RT_8192S_FIRMWARE_HDR_EXCLUDE_PRI_SIZE;
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break;
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||||
default:
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RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
|
||||
("Unexpected Download step!!\n"));
|
||||
goto fail;
|
||||
break;
|
||||
}
|
||||
|
||||
/* <2> Download image file */
|
||||
rtstatus = _rtl92s_firmware_downloadcode(hw, puc_mappedfile,
|
||||
ul_filelength);
|
||||
|
||||
if (rtstatus != true) {
|
||||
RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("fail!\n"));
|
||||
goto fail;
|
||||
}
|
||||
|
||||
/* <3> Check whether load FW process is ready */
|
||||
rtstatus = _rtl92s_firmware_checkready(hw, fwstatus);
|
||||
if (rtstatus != true) {
|
||||
RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("fail!\n"));
|
||||
goto fail;
|
||||
}
|
||||
|
||||
fwstatus = _rtl92s_firmware_get_nextstatus(firmware->fwstatus);
|
||||
}
|
||||
|
||||
return rtstatus;
|
||||
fail:
|
||||
return 0;
|
||||
}
|
||||
|
||||
static u32 _rtl92s_fill_h2c_cmd(struct sk_buff *skb, u32 h2cbufferlen,
|
||||
u32 cmd_num, u32 *pelement_id, u32 *pcmd_len,
|
||||
u8 **pcmb_buffer, u8 *cmd_start_seq)
|
||||
{
|
||||
u32 totallen = 0, len = 0, tx_desclen = 0;
|
||||
u32 pre_continueoffset = 0;
|
||||
u8 *ph2c_buffer;
|
||||
u8 i = 0;
|
||||
|
||||
do {
|
||||
/* 8 - Byte aligment */
|
||||
len = H2C_TX_CMD_HDR_LEN + N_BYTE_ALIGMENT(pcmd_len[i], 8);
|
||||
|
||||
/* Buffer length is not enough */
|
||||
if (h2cbufferlen < totallen + len + tx_desclen)
|
||||
break;
|
||||
|
||||
/* Clear content */
|
||||
ph2c_buffer = (u8 *)skb_put(skb, (u32)len);
|
||||
memset((ph2c_buffer + totallen + tx_desclen), 0, len);
|
||||
|
||||
/* CMD len */
|
||||
SET_BITS_TO_LE_4BYTE((ph2c_buffer + totallen + tx_desclen),
|
||||
0, 16, pcmd_len[i]);
|
||||
|
||||
/* CMD ID */
|
||||
SET_BITS_TO_LE_4BYTE((ph2c_buffer + totallen + tx_desclen),
|
||||
16, 8, pelement_id[i]);
|
||||
|
||||
/* CMD Sequence */
|
||||
*cmd_start_seq = *cmd_start_seq % 0x80;
|
||||
SET_BITS_TO_LE_4BYTE((ph2c_buffer + totallen + tx_desclen),
|
||||
24, 7, *cmd_start_seq);
|
||||
++*cmd_start_seq;
|
||||
|
||||
/* Copy memory */
|
||||
memcpy((ph2c_buffer + totallen + tx_desclen +
|
||||
H2C_TX_CMD_HDR_LEN), pcmb_buffer[i], pcmd_len[i]);
|
||||
|
||||
/* CMD continue */
|
||||
/* set the continue in prevoius cmd. */
|
||||
if (i < cmd_num - 1)
|
||||
SET_BITS_TO_LE_4BYTE((ph2c_buffer + pre_continueoffset),
|
||||
31, 1, 1);
|
||||
|
||||
pre_continueoffset = totallen;
|
||||
|
||||
totallen += len;
|
||||
} while (++i < cmd_num);
|
||||
|
||||
return totallen;
|
||||
}
|
||||
|
||||
static u32 _rtl92s_get_h2c_cmdlen(u32 h2cbufferlen, u32 cmd_num, u32 *pcmd_len)
|
||||
{
|
||||
u32 totallen = 0, len = 0, tx_desclen = 0;
|
||||
u8 i = 0;
|
||||
|
||||
do {
|
||||
/* 8 - Byte aligment */
|
||||
len = H2C_TX_CMD_HDR_LEN + N_BYTE_ALIGMENT(pcmd_len[i], 8);
|
||||
|
||||
/* Buffer length is not enough */
|
||||
if (h2cbufferlen < totallen + len + tx_desclen)
|
||||
break;
|
||||
|
||||
totallen += len;
|
||||
} while (++i < cmd_num);
|
||||
|
||||
return totallen + tx_desclen;
|
||||
}
|
||||
|
||||
static bool _rtl92s_firmware_set_h2c_cmd(struct ieee80211_hw *hw, u8 h2c_cmd,
|
||||
u8 *pcmd_buffer)
|
||||
{
|
||||
struct rtl_priv *rtlpriv = rtl_priv(hw);
|
||||
struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
|
||||
struct rtl_tcb_desc *cb_desc;
|
||||
struct sk_buff *skb;
|
||||
u32 element_id = 0;
|
||||
u32 cmd_len = 0;
|
||||
u32 len;
|
||||
|
||||
switch (h2c_cmd) {
|
||||
case FW_H2C_SETPWRMODE:
|
||||
element_id = H2C_SETPWRMODE_CMD ;
|
||||
cmd_len = sizeof(struct h2c_set_pwrmode_parm);
|
||||
break;
|
||||
case FW_H2C_JOINBSSRPT:
|
||||
element_id = H2C_JOINBSSRPT_CMD;
|
||||
cmd_len = sizeof(struct h2c_joinbss_rpt_parm);
|
||||
break;
|
||||
case FW_H2C_WOWLAN_UPDATE_GTK:
|
||||
element_id = H2C_WOWLAN_UPDATE_GTK_CMD;
|
||||
cmd_len = sizeof(struct h2c_wpa_two_way_parm);
|
||||
break;
|
||||
case FW_H2C_WOWLAN_UPDATE_IV:
|
||||
element_id = H2C_WOWLAN_UPDATE_IV_CMD;
|
||||
cmd_len = sizeof(unsigned long long);
|
||||
break;
|
||||
case FW_H2C_WOWLAN_OFFLOAD:
|
||||
element_id = H2C_WOWLAN_FW_OFFLOAD;
|
||||
cmd_len = sizeof(u8);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
len = _rtl92s_get_h2c_cmdlen(MAX_TRANSMIT_BUFFER_SIZE, 1, &cmd_len);
|
||||
skb = dev_alloc_skb(len);
|
||||
cb_desc = (struct rtl_tcb_desc *)(skb->cb);
|
||||
cb_desc->queue_index = TXCMD_QUEUE;
|
||||
cb_desc->cmd_or_init = DESC_PACKET_TYPE_NORMAL;
|
||||
cb_desc->last_inipkt = false;
|
||||
|
||||
_rtl92s_fill_h2c_cmd(skb, MAX_TRANSMIT_BUFFER_SIZE, 1, &element_id,
|
||||
&cmd_len, &pcmd_buffer, &rtlhal->h2c_txcmd_seq);
|
||||
_rtl92s_cmd_send_packet(hw, skb, false);
|
||||
rtlpriv->cfg->ops->tx_polling(hw, TXCMD_QUEUE);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
void rtl92s_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 Mode)
|
||||
{
|
||||
struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
|
||||
struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
|
||||
struct h2c_set_pwrmode_parm pwrmode;
|
||||
u16 max_wakeup_period = 0;
|
||||
|
||||
pwrmode.mode = Mode;
|
||||
pwrmode.flag_low_traffic_en = 0;
|
||||
pwrmode.flag_lpnav_en = 0;
|
||||
pwrmode.flag_rf_low_snr_en = 0;
|
||||
pwrmode.flag_dps_en = 0;
|
||||
pwrmode.bcn_rx_en = 0;
|
||||
pwrmode.bcn_to = 0;
|
||||
SET_BITS_TO_LE_2BYTE((u8 *)(&pwrmode) + 8, 0, 16,
|
||||
mac->vif->bss_conf.beacon_int);
|
||||
pwrmode.app_itv = 0;
|
||||
pwrmode.awake_bcn_itvl = ppsc->reg_max_lps_awakeintvl;
|
||||
pwrmode.smart_ps = 1;
|
||||
pwrmode.bcn_pass_period = 10;
|
||||
|
||||
/* Set beacon pass count */
|
||||
if (pwrmode.mode == FW_PS_MIN_MODE)
|
||||
max_wakeup_period = mac->vif->bss_conf.beacon_int;
|
||||
else if (pwrmode.mode == FW_PS_MAX_MODE)
|
||||
max_wakeup_period = mac->vif->bss_conf.beacon_int *
|
||||
mac->vif->bss_conf.dtim_period;
|
||||
|
||||
if (max_wakeup_period >= 500)
|
||||
pwrmode.bcn_pass_cnt = 1;
|
||||
else if ((max_wakeup_period >= 300) && (max_wakeup_period < 500))
|
||||
pwrmode.bcn_pass_cnt = 2;
|
||||
else if ((max_wakeup_period >= 200) && (max_wakeup_period < 300))
|
||||
pwrmode.bcn_pass_cnt = 3;
|
||||
else if ((max_wakeup_period >= 20) && (max_wakeup_period < 200))
|
||||
pwrmode.bcn_pass_cnt = 5;
|
||||
else
|
||||
pwrmode.bcn_pass_cnt = 1;
|
||||
|
||||
_rtl92s_firmware_set_h2c_cmd(hw, FW_H2C_SETPWRMODE, (u8 *)&pwrmode);
|
||||
|
||||
}
|
||||
|
||||
void rtl92s_set_fw_joinbss_report_cmd(struct ieee80211_hw *hw,
|
||||
u8 mstatus, u8 ps_qosinfo)
|
||||
{
|
||||
struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
|
||||
struct h2c_joinbss_rpt_parm joinbss_rpt;
|
||||
|
||||
joinbss_rpt.opmode = mstatus;
|
||||
joinbss_rpt.ps_qos_info = ps_qosinfo;
|
||||
joinbss_rpt.bssid[0] = mac->bssid[0];
|
||||
joinbss_rpt.bssid[1] = mac->bssid[1];
|
||||
joinbss_rpt.bssid[2] = mac->bssid[2];
|
||||
joinbss_rpt.bssid[3] = mac->bssid[3];
|
||||
joinbss_rpt.bssid[4] = mac->bssid[4];
|
||||
joinbss_rpt.bssid[5] = mac->bssid[5];
|
||||
SET_BITS_TO_LE_2BYTE((u8 *)(&joinbss_rpt) + 8, 0, 16,
|
||||
mac->vif->bss_conf.beacon_int);
|
||||
SET_BITS_TO_LE_2BYTE((u8 *)(&joinbss_rpt) + 10, 0, 16, mac->assoc_id);
|
||||
|
||||
_rtl92s_firmware_set_h2c_cmd(hw, FW_H2C_JOINBSSRPT, (u8 *)&joinbss_rpt);
|
||||
}
|
||||
|
||||
375
drivers/net/wireless/rtlwifi/rtl8192se/fw.h
Normal file
375
drivers/net/wireless/rtlwifi/rtl8192se/fw.h
Normal file
@ -0,0 +1,375 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2009-2010 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
* The full GNU General Public License is included in this distribution in the
|
||||
* file called LICENSE.
|
||||
*
|
||||
* Contact Information:
|
||||
* wlanfae <wlanfae@realtek.com>
|
||||
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
|
||||
* Hsinchu 300, Taiwan.
|
||||
*
|
||||
* Larry Finger <Larry.Finger@lwfinger.net>
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __REALTEK_FIRMWARE92S_H__
|
||||
#define __REALTEK_FIRMWARE92S_H__
|
||||
|
||||
#define RTL8190_MAX_FIRMWARE_CODE_SIZE 64000
|
||||
#define RTL8190_CPU_START_OFFSET 0x80
|
||||
/* Firmware Local buffer size. 64k */
|
||||
#define MAX_FIRMWARE_CODE_SIZE 0xFF00
|
||||
|
||||
#define RT_8192S_FIRMWARE_HDR_SIZE 80
|
||||
#define RT_8192S_FIRMWARE_HDR_EXCLUDE_PRI_SIZE 32
|
||||
|
||||
/* support till 64 bit bus width OS */
|
||||
#define MAX_DEV_ADDR_SIZE 8
|
||||
#define MAX_FIRMWARE_INFORMATION_SIZE 32
|
||||
#define MAX_802_11_HEADER_LENGTH (40 + \
|
||||
MAX_FIRMWARE_INFORMATION_SIZE)
|
||||
#define ENCRYPTION_MAX_OVERHEAD 128
|
||||
#define MAX_FRAGMENT_COUNT 8
|
||||
#define MAX_TRANSMIT_BUFFER_SIZE (1600 + \
|
||||
(MAX_802_11_HEADER_LENGTH + \
|
||||
ENCRYPTION_MAX_OVERHEAD) *\
|
||||
MAX_FRAGMENT_COUNT)
|
||||
|
||||
#define H2C_TX_CMD_HDR_LEN 8
|
||||
|
||||
/* The following DM control code are for Reg0x364, */
|
||||
#define FW_DIG_ENABLE_CTL BIT(0)
|
||||
#define FW_HIGH_PWR_ENABLE_CTL BIT(1)
|
||||
#define FW_SS_CTL BIT(2)
|
||||
#define FW_RA_INIT_CTL BIT(3)
|
||||
#define FW_RA_BG_CTL BIT(4)
|
||||
#define FW_RA_N_CTL BIT(5)
|
||||
#define FW_PWR_TRK_CTL BIT(6)
|
||||
#define FW_IQK_CTL BIT(7)
|
||||
#define FW_FA_CTL BIT(8)
|
||||
#define FW_DRIVER_CTRL_DM_CTL BIT(9)
|
||||
#define FW_PAPE_CTL_BY_SW_HW BIT(10)
|
||||
#define FW_DISABLE_ALL_DM 0
|
||||
#define FW_PWR_TRK_PARAM_CLR 0x0000ffff
|
||||
#define FW_RA_PARAM_CLR 0xffff0000
|
||||
|
||||
enum desc_packet_type {
|
||||
DESC_PACKET_TYPE_INIT = 0,
|
||||
DESC_PACKET_TYPE_NORMAL = 1,
|
||||
};
|
||||
|
||||
/* 8-bytes alignment required */
|
||||
struct fw_priv {
|
||||
/* --- long word 0 ---- */
|
||||
/* 0x12: CE product, 0x92: IT product */
|
||||
u8 signature_0;
|
||||
/* 0x87: CE product, 0x81: IT product */
|
||||
u8 signature_1;
|
||||
/* 0x81: PCI-AP, 01:PCIe, 02: 92S-U,
|
||||
* 0x82: USB-AP, 0x12: 72S-U, 03:SDIO */
|
||||
u8 hci_sel;
|
||||
/* the same value as reigster value */
|
||||
u8 chip_version;
|
||||
/* customer ID low byte */
|
||||
u8 customer_id_0;
|
||||
/* customer ID high byte */
|
||||
u8 customer_id_1;
|
||||
/* 0x11: 1T1R, 0x12: 1T2R,
|
||||
* 0x92: 1T2R turbo, 0x22: 2T2R */
|
||||
u8 rf_config;
|
||||
/* 4: 4EP, 6: 6EP, 11: 11EP */
|
||||
u8 usb_ep_num;
|
||||
|
||||
/* --- long word 1 ---- */
|
||||
/* regulatory class bit map 0 */
|
||||
u8 regulatory_class_0;
|
||||
/* regulatory class bit map 1 */
|
||||
u8 regulatory_class_1;
|
||||
/* regulatory class bit map 2 */
|
||||
u8 regulatory_class_2;
|
||||
/* regulatory class bit map 3 */
|
||||
u8 regulatory_class_3;
|
||||
/* 0:SWSI, 1:HWSI, 2:HWPI */
|
||||
u8 rfintfs;
|
||||
u8 def_nettype;
|
||||
u8 rsvd010;
|
||||
u8 rsvd011;
|
||||
|
||||
/* --- long word 2 ---- */
|
||||
/* 0x00: normal, 0x03: MACLBK, 0x01: PHYLBK */
|
||||
u8 lbk_mode;
|
||||
/* 1: for MP use, 0: for normal
|
||||
* driver (to be discussed) */
|
||||
u8 mp_mode;
|
||||
u8 rsvd020;
|
||||
u8 rsvd021;
|
||||
u8 rsvd022;
|
||||
u8 rsvd023;
|
||||
u8 rsvd024;
|
||||
u8 rsvd025;
|
||||
|
||||
/* --- long word 3 ---- */
|
||||
/* QoS enable */
|
||||
u8 qos_en;
|
||||
/* 40MHz BW enable */
|
||||
/* 4181 convert AMSDU to AMPDU, 0: disable */
|
||||
u8 bw_40mhz_en;
|
||||
u8 amsdu2ampdu_en;
|
||||
/* 11n AMPDU enable */
|
||||
u8 ampdu_en;
|
||||
/* FW offloads, 0: driver handles */
|
||||
u8 rate_control_offload;
|
||||
/* FW offloads, 0: driver handles */
|
||||
u8 aggregation_offload;
|
||||
u8 rsvd030;
|
||||
u8 rsvd031;
|
||||
|
||||
/* --- long word 4 ---- */
|
||||
/* 1. FW offloads, 0: driver handles */
|
||||
u8 beacon_offload;
|
||||
/* 2. FW offloads, 0: driver handles */
|
||||
u8 mlme_offload;
|
||||
/* 3. FW offloads, 0: driver handles */
|
||||
u8 hwpc_offload;
|
||||
/* 4. FW offloads, 0: driver handles */
|
||||
u8 tcp_checksum_offload;
|
||||
/* 5. FW offloads, 0: driver handles */
|
||||
u8 tcp_offload;
|
||||
/* 6. FW offloads, 0: driver handles */
|
||||
u8 ps_control_offload;
|
||||
/* 7. FW offloads, 0: driver handles */
|
||||
u8 wwlan_offload;
|
||||
u8 rsvd040;
|
||||
|
||||
/* --- long word 5 ---- */
|
||||
/* tcp tx packet length low byte */
|
||||
u8 tcp_tx_frame_len_L;
|
||||
/* tcp tx packet length high byte */
|
||||
u8 tcp_tx_frame_len_H;
|
||||
/* tcp rx packet length low byte */
|
||||
u8 tcp_rx_frame_len_L;
|
||||
/* tcp rx packet length high byte */
|
||||
u8 tcp_rx_frame_len_H;
|
||||
u8 rsvd050;
|
||||
u8 rsvd051;
|
||||
u8 rsvd052;
|
||||
u8 rsvd053;
|
||||
};
|
||||
|
||||
/* 8-byte alinment required */
|
||||
struct fw_hdr {
|
||||
|
||||
/* --- LONG WORD 0 ---- */
|
||||
u16 signature;
|
||||
/* 0x8000 ~ 0x8FFF for FPGA version,
|
||||
* 0x0000 ~ 0x7FFF for ASIC version, */
|
||||
u16 version;
|
||||
/* define the size of boot loader */
|
||||
u32 dmem_size;
|
||||
|
||||
|
||||
/* --- LONG WORD 1 ---- */
|
||||
/* define the size of FW in IMEM */
|
||||
u32 img_imem_size;
|
||||
/* define the size of FW in SRAM */
|
||||
u32 img_sram_size;
|
||||
|
||||
/* --- LONG WORD 2 ---- */
|
||||
/* define the size of DMEM variable */
|
||||
u32 fw_priv_size;
|
||||
u32 rsvd0;
|
||||
|
||||
/* --- LONG WORD 3 ---- */
|
||||
u32 rsvd1;
|
||||
u32 rsvd2;
|
||||
|
||||
struct fw_priv fwpriv;
|
||||
|
||||
} ;
|
||||
|
||||
enum fw_status {
|
||||
FW_STATUS_INIT = 0,
|
||||
FW_STATUS_LOAD_IMEM = 1,
|
||||
FW_STATUS_LOAD_EMEM = 2,
|
||||
FW_STATUS_LOAD_DMEM = 3,
|
||||
FW_STATUS_READY = 4,
|
||||
};
|
||||
|
||||
struct rt_firmware {
|
||||
struct fw_hdr *pfwheader;
|
||||
enum fw_status fwstatus;
|
||||
u16 firmwareversion;
|
||||
u8 fw_imem[RTL8190_MAX_FIRMWARE_CODE_SIZE];
|
||||
u8 fw_emem[RTL8190_MAX_FIRMWARE_CODE_SIZE];
|
||||
u32 fw_imem_len;
|
||||
u32 fw_emem_len;
|
||||
u8 sz_fw_tmpbuffer[164000];
|
||||
u32 sz_fw_tmpbufferlen;
|
||||
u16 cmdpacket_fragthresold;
|
||||
};
|
||||
|
||||
struct h2c_set_pwrmode_parm {
|
||||
u8 mode;
|
||||
u8 flag_low_traffic_en;
|
||||
u8 flag_lpnav_en;
|
||||
u8 flag_rf_low_snr_en;
|
||||
/* 1: dps, 0: 32k */
|
||||
u8 flag_dps_en;
|
||||
u8 bcn_rx_en;
|
||||
u8 bcn_pass_cnt;
|
||||
/* beacon TO (ms). ¡§=0¡¨ no limit. */
|
||||
u8 bcn_to;
|
||||
u16 bcn_itv;
|
||||
/* only for VOIP mode. */
|
||||
u8 app_itv;
|
||||
u8 awake_bcn_itvl;
|
||||
u8 smart_ps;
|
||||
/* unit: 100 ms */
|
||||
u8 bcn_pass_period;
|
||||
};
|
||||
|
||||
struct h2c_joinbss_rpt_parm {
|
||||
u8 opmode;
|
||||
u8 ps_qos_info;
|
||||
u8 bssid[6];
|
||||
u16 bcnitv;
|
||||
u16 aid;
|
||||
} ;
|
||||
|
||||
struct h2c_wpa_ptk {
|
||||
/* EAPOL-Key Key Confirmation Key (KCK) */
|
||||
u8 kck[16];
|
||||
/* EAPOL-Key Key Encryption Key (KEK) */
|
||||
u8 kek[16];
|
||||
/* Temporal Key 1 (TK1) */
|
||||
u8 tk1[16];
|
||||
union {
|
||||
/* Temporal Key 2 (TK2) */
|
||||
u8 tk2[16];
|
||||
struct {
|
||||
u8 tx_mic_key[8];
|
||||
u8 rx_mic_key[8];
|
||||
} athu;
|
||||
} u;
|
||||
};
|
||||
|
||||
struct h2c_wpa_two_way_parm {
|
||||
/* algorithm TKIP or AES */
|
||||
u8 pairwise_en_alg;
|
||||
u8 group_en_alg;
|
||||
struct h2c_wpa_ptk wpa_ptk_value;
|
||||
} ;
|
||||
|
||||
enum h2c_cmd {
|
||||
FW_H2C_SETPWRMODE = 0,
|
||||
FW_H2C_JOINBSSRPT = 1,
|
||||
FW_H2C_WOWLAN_UPDATE_GTK = 2,
|
||||
FW_H2C_WOWLAN_UPDATE_IV = 3,
|
||||
FW_H2C_WOWLAN_OFFLOAD = 4,
|
||||
};
|
||||
|
||||
enum fw_h2c_cmd {
|
||||
H2C_READ_MACREG_CMD, /*0*/
|
||||
H2C_WRITE_MACREG_CMD,
|
||||
H2C_READBB_CMD,
|
||||
H2C_WRITEBB_CMD,
|
||||
H2C_READRF_CMD,
|
||||
H2C_WRITERF_CMD, /*5*/
|
||||
H2C_READ_EEPROM_CMD,
|
||||
H2C_WRITE_EEPROM_CMD,
|
||||
H2C_READ_EFUSE_CMD,
|
||||
H2C_WRITE_EFUSE_CMD,
|
||||
H2C_READ_CAM_CMD, /*10*/
|
||||
H2C_WRITE_CAM_CMD,
|
||||
H2C_SETBCNITV_CMD,
|
||||
H2C_SETMBIDCFG_CMD,
|
||||
H2C_JOINBSS_CMD,
|
||||
H2C_DISCONNECT_CMD, /*15*/
|
||||
H2C_CREATEBSS_CMD,
|
||||
H2C_SETOPMode_CMD,
|
||||
H2C_SITESURVEY_CMD,
|
||||
H2C_SETAUTH_CMD,
|
||||
H2C_SETKEY_CMD, /*20*/
|
||||
H2C_SETSTAKEY_CMD,
|
||||
H2C_SETASSOCSTA_CMD,
|
||||
H2C_DELASSOCSTA_CMD,
|
||||
H2C_SETSTAPWRSTATE_CMD,
|
||||
H2C_SETBASICRATE_CMD, /*25*/
|
||||
H2C_GETBASICRATE_CMD,
|
||||
H2C_SETDATARATE_CMD,
|
||||
H2C_GETDATARATE_CMD,
|
||||
H2C_SETPHYINFO_CMD,
|
||||
H2C_GETPHYINFO_CMD, /*30*/
|
||||
H2C_SETPHY_CMD,
|
||||
H2C_GETPHY_CMD,
|
||||
H2C_READRSSI_CMD,
|
||||
H2C_READGAIN_CMD,
|
||||
H2C_SETATIM_CMD, /*35*/
|
||||
H2C_SETPWRMODE_CMD,
|
||||
H2C_JOINBSSRPT_CMD,
|
||||
H2C_SETRATABLE_CMD,
|
||||
H2C_GETRATABLE_CMD,
|
||||
H2C_GETCCXREPORT_CMD, /*40*/
|
||||
H2C_GETDTMREPORT_CMD,
|
||||
H2C_GETTXRATESTATICS_CMD,
|
||||
H2C_SETUSBSUSPEND_CMD,
|
||||
H2C_SETH2CLBK_CMD,
|
||||
H2C_TMP1, /*45*/
|
||||
H2C_WOWLAN_UPDATE_GTK_CMD,
|
||||
H2C_WOWLAN_FW_OFFLOAD,
|
||||
H2C_TMP2,
|
||||
H2C_TMP3,
|
||||
H2C_WOWLAN_UPDATE_IV_CMD, /*50*/
|
||||
H2C_TMP4,
|
||||
MAX_H2CCMD /*52*/
|
||||
};
|
||||
|
||||
/* The following macros are used for FW
|
||||
* CMD map and parameter updated. */
|
||||
#define FW_CMD_IO_CLR(rtlpriv, _Bit) \
|
||||
do { \
|
||||
udelay(1000); \
|
||||
rtlpriv->rtlhal.fwcmd_iomap &= (~_Bit); \
|
||||
} while (0);
|
||||
|
||||
#define FW_CMD_IO_UPDATE(rtlpriv, _val) \
|
||||
rtlpriv->rtlhal.fwcmd_iomap = _val;
|
||||
|
||||
#define FW_CMD_IO_SET(rtlpriv, _val) \
|
||||
do { \
|
||||
rtl_write_word(rtlpriv, LBUS_MON_ADDR, (u16)_val); \
|
||||
FW_CMD_IO_UPDATE(rtlpriv, _val); \
|
||||
} while (0);
|
||||
|
||||
#define FW_CMD_PARA_SET(rtlpriv, _val) \
|
||||
do { \
|
||||
rtl_write_dword(rtlpriv, LBUS_ADDR_MASK, _val); \
|
||||
rtlpriv->rtlhal.fwcmd_ioparam = _val; \
|
||||
} while (0);
|
||||
|
||||
#define FW_CMD_IO_QUERY(rtlpriv) \
|
||||
(u16)(rtlpriv->rtlhal.fwcmd_iomap)
|
||||
#define FW_CMD_IO_PARA_QUERY(rtlpriv) \
|
||||
((u32)(rtlpriv->rtlhal.fwcmd_ioparam))
|
||||
|
||||
int rtl92s_download_fw(struct ieee80211_hw *hw);
|
||||
void rtl92s_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode);
|
||||
void rtl92s_set_fw_joinbss_report_cmd(struct ieee80211_hw *hw,
|
||||
u8 mstatus, u8 ps_qosinfo);
|
||||
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue
Block a user