arm64/sysreg: Standardise naming for ID_AA64MMFR1_EL1 fields
In preparation for converting the ID_AA64MMFR1_EL1 system register defines to automatic generation, rename them to follow the conventions used by other automatically generated registers: * Add _EL1 in the register name. * Rename fields to match the names in the ARM ARM: * LOR -> LO * HPD -> HPDS * VHE -> VH * HADBS -> HAFDBS * SPECSEI -> SpecSEI * VMIDBITS -> VMIDBits There should be no functional change as a result of this patch. Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com> Signed-off-by: Mark Brown <broonie@kernel.org> Reviewed-by: Kristina Martsenko <kristina.martsenko@arm.com> Link: https://lore.kernel.org/r/20220905225425.1871461-11-broonie@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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@ -868,14 +868,14 @@ static inline bool cpu_has_hw_af(void)
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mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
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return cpuid_feature_extract_unsigned_field(mmfr1,
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ID_AA64MMFR1_HADBS_SHIFT);
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ID_AA64MMFR1_EL1_HAFDBS_SHIFT);
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}
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static inline bool cpu_has_pan(void)
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{
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u64 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
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return cpuid_feature_extract_unsigned_field(mmfr1,
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ID_AA64MMFR1_PAN_SHIFT);
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ID_AA64MMFR1_EL1_PAN_SHIFT);
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}
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#ifdef CONFIG_ARM64_AMU_EXTN
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@ -896,8 +896,8 @@ static inline unsigned int get_vmid_bits(u64 mmfr1)
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int vmid_bits;
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vmid_bits = cpuid_feature_extract_unsigned_field(mmfr1,
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ID_AA64MMFR1_VMIDBITS_SHIFT);
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if (vmid_bits == ID_AA64MMFR1_VMIDBITS_16)
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ID_AA64MMFR1_EL1_VMIDBits_SHIFT);
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if (vmid_bits == ID_AA64MMFR1_EL1_VMIDBits_16)
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return 16;
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/*
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@ -83,7 +83,7 @@
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/* LORegions */
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.macro __init_el2_lor
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mrs x1, id_aa64mmfr1_el1
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ubfx x0, x1, #ID_AA64MMFR1_LOR_SHIFT, 4
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ubfx x0, x1, #ID_AA64MMFR1_EL1_LO_SHIFT, 4
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cbz x0, .Lskip_lor_\@
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msr_s SYS_LORC_EL1, xzr
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.Lskip_lor_\@:
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@ -783,26 +783,26 @@
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#endif
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/* id_aa64mmfr1 */
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#define ID_AA64MMFR1_ECBHB_SHIFT 60
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#define ID_AA64MMFR1_TIDCP1_SHIFT 52
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#define ID_AA64MMFR1_HCX_SHIFT 40
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#define ID_AA64MMFR1_AFP_SHIFT 44
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#define ID_AA64MMFR1_ETS_SHIFT 36
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#define ID_AA64MMFR1_TWED_SHIFT 32
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#define ID_AA64MMFR1_XNX_SHIFT 28
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#define ID_AA64MMFR1_SPECSEI_SHIFT 24
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#define ID_AA64MMFR1_PAN_SHIFT 20
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#define ID_AA64MMFR1_LOR_SHIFT 16
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#define ID_AA64MMFR1_HPD_SHIFT 12
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#define ID_AA64MMFR1_VHE_SHIFT 8
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#define ID_AA64MMFR1_VMIDBITS_SHIFT 4
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#define ID_AA64MMFR1_HADBS_SHIFT 0
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#define ID_AA64MMFR1_EL1_ECBHB_SHIFT 60
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#define ID_AA64MMFR1_EL1_TIDCP1_SHIFT 52
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#define ID_AA64MMFR1_EL1_HCX_SHIFT 40
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#define ID_AA64MMFR1_EL1_AFP_SHIFT 44
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#define ID_AA64MMFR1_EL1_ETS_SHIFT 36
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#define ID_AA64MMFR1_EL1_TWED_SHIFT 32
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#define ID_AA64MMFR1_EL1_XNX_SHIFT 28
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#define ID_AA64MMFR1_EL1_SpecSEI_SHIFT 24
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#define ID_AA64MMFR1_EL1_PAN_SHIFT 20
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#define ID_AA64MMFR1_EL1_LO_SHIFT 16
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#define ID_AA64MMFR1_EL1_HPDS_SHIFT 12
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#define ID_AA64MMFR1_EL1_VH_SHIFT 8
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#define ID_AA64MMFR1_EL1_VMIDBits_SHIFT 4
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#define ID_AA64MMFR1_EL1_HAFDBS_SHIFT 0
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#define ID_AA64MMFR1_VMIDBITS_8 0
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#define ID_AA64MMFR1_VMIDBITS_16 2
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#define ID_AA64MMFR1_EL1_VMIDBits_8 0
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#define ID_AA64MMFR1_EL1_VMIDBits_16 2
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#define ID_AA64MMFR1_TIDCP1_NI 0
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#define ID_AA64MMFR1_TIDCP1_IMP 1
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#define ID_AA64MMFR1_EL1_TIDCP1_NI 0
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#define ID_AA64MMFR1_EL1_TIDCP1_IMP 1
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/* id_aa64mmfr2 */
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#define ID_AA64MMFR2_EL1_E0PD_SHIFT 60
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@ -362,18 +362,18 @@ static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
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};
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static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
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ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_TIDCP1_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_AFP_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_ETS_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_TWED_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_XNX_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_SPECSEI_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TIDCP1_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_AFP_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_ETS_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TWED_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_XNX_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_EL1_SpecSEI_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_PAN_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_LO_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HPDS_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VH_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VMIDBits_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HAFDBS_SHIFT, 4, 0),
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ARM64_FTR_END,
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};
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@ -2116,7 +2116,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
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.type = ARM64_CPUCAP_SYSTEM_FEATURE,
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.matches = has_cpuid_feature,
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.sys_reg = SYS_ID_AA64MMFR1_EL1,
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.field_pos = ID_AA64MMFR1_PAN_SHIFT,
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.field_pos = ID_AA64MMFR1_EL1_PAN_SHIFT,
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.field_width = 4,
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.sign = FTR_UNSIGNED,
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.min_field_value = 1,
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@ -2130,7 +2130,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
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.type = ARM64_CPUCAP_SYSTEM_FEATURE,
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.matches = has_cpuid_feature,
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.sys_reg = SYS_ID_AA64MMFR1_EL1,
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.field_pos = ID_AA64MMFR1_PAN_SHIFT,
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.field_pos = ID_AA64MMFR1_EL1_PAN_SHIFT,
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.field_width = 4,
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.sign = FTR_UNSIGNED,
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.min_field_value = 3,
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@ -2344,7 +2344,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
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.capability = ARM64_HW_DBM,
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.sys_reg = SYS_ID_AA64MMFR1_EL1,
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.sign = FTR_UNSIGNED,
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.field_pos = ID_AA64MMFR1_HADBS_SHIFT,
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.field_pos = ID_AA64MMFR1_EL1_HAFDBS_SHIFT,
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.field_width = 4,
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.min_field_value = 2,
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.matches = has_hw_dbm,
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@ -2614,9 +2614,9 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
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.type = ARM64_CPUCAP_SYSTEM_FEATURE,
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.sys_reg = SYS_ID_AA64MMFR1_EL1,
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.sign = FTR_UNSIGNED,
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.field_pos = ID_AA64MMFR1_TIDCP1_SHIFT,
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.field_pos = ID_AA64MMFR1_EL1_TIDCP1_SHIFT,
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.field_width = 4,
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.min_field_value = ID_AA64MMFR1_TIDCP1_IMP,
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.min_field_value = ID_AA64MMFR1_EL1_TIDCP1_IMP,
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.matches = has_cpuid_feature,
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.cpu_enable = cpu_trap_el0_impdef,
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},
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@ -2752,7 +2752,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
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HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_EL1_MTE_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_EL1_MTE_ASYMM, CAP_HWCAP, KERNEL_HWCAP_MTE3),
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#endif /* CONFIG_ARM64_MTE */
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HWCAP_CAP(SYS_ID_AA64MMFR0_EL1, ID_AA64MMFR0_EL1_ECV_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ECV),
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HWCAP_CAP(SYS_ID_AA64MMFR1_EL1, ID_AA64MMFR1_AFP_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AFP),
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HWCAP_CAP(SYS_ID_AA64MMFR1_EL1, ID_AA64MMFR1_EL1_AFP_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AFP),
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HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_RPRES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RPRES),
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HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_WFxT_SHIFT, 4, FTR_UNSIGNED, ID_AA64ISAR2_EL1_WFxT_IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT),
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#ifdef CONFIG_ARM64_SME
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@ -142,7 +142,7 @@ SYM_CODE_START_LOCAL(__finalise_el2)
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msr_s SYS_SMPRIMAP_EL2, xzr // Make all priorities equal
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mrs x1, id_aa64mmfr1_el1 // HCRX_EL2 present?
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ubfx x1, x1, #ID_AA64MMFR1_HCX_SHIFT, #4
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ubfx x1, x1, #ID_AA64MMFR1_EL1_HCX_SHIFT, #4
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cbz x1, .Lskip_sme
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mrs_s x1, SYS_HCRX_EL2
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@ -157,7 +157,7 @@ SYM_CODE_START_LOCAL(__finalise_el2)
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tbnz x1, #0, 1f
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// Needs to be VHE capable, obviously
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check_override id_aa64mmfr1 ID_AA64MMFR1_VHE_SHIFT 2f 1f
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check_override id_aa64mmfr1 ID_AA64MMFR1_EL1_VH_SHIFT 2f 1f
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1: mov_q x0, HVC_STUB_ERR
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eret
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@ -50,7 +50,7 @@ static const struct ftr_set_desc mmfr1 __initconst = {
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.name = "id_aa64mmfr1",
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.override = &id_aa64mmfr1_override,
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.fields = {
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FIELD("vh", ID_AA64MMFR1_VHE_SHIFT, mmfr1_vh_filter),
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FIELD("vh", ID_AA64MMFR1_EL1_VH_SHIFT, mmfr1_vh_filter),
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{}
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},
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};
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@ -945,7 +945,7 @@ static bool supports_ecbhb(int scope)
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mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
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return cpuid_feature_extract_unsigned_field(mmfr1,
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ID_AA64MMFR1_ECBHB_SHIFT);
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ID_AA64MMFR1_EL1_ECBHB_SHIFT);
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}
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bool is_spectre_bhb_affected(const struct arm64_cpu_capabilities *entry,
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@ -100,12 +100,12 @@
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* - Enhanced Translation Synchronization
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*/
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#define PVM_ID_AA64MMFR1_ALLOW (\
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ARM64_FEATURE_MASK(ID_AA64MMFR1_HADBS) | \
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ARM64_FEATURE_MASK(ID_AA64MMFR1_VMIDBITS) | \
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ARM64_FEATURE_MASK(ID_AA64MMFR1_HPD) | \
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ARM64_FEATURE_MASK(ID_AA64MMFR1_PAN) | \
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ARM64_FEATURE_MASK(ID_AA64MMFR1_SPECSEI) | \
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ARM64_FEATURE_MASK(ID_AA64MMFR1_ETS) \
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ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_HAFDBS) | \
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ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_VMIDBits) | \
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ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_HPDS) | \
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ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_PAN) | \
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ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_SpecSEI) | \
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ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_ETS) \
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)
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/*
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@ -143,7 +143,7 @@ static void pvm_init_traps_aa64mmfr1(struct kvm_vcpu *vcpu)
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u64 hcr_set = 0;
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/* Trap LOR */
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if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64MMFR1_LOR), feature_ids))
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if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_LO), feature_ids))
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hcr_set |= HCR_TLOR;
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vcpu->arch.hcr_el2 |= hcr_set;
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@ -273,7 +273,7 @@ static bool trap_loregion(struct kvm_vcpu *vcpu,
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u64 val = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
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u32 sr = reg_to_encoding(r);
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if (!(val & (0xfUL << ID_AA64MMFR1_LOR_SHIFT))) {
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if (!(val & (0xfUL << ID_AA64MMFR1_EL1_LO_SHIFT))) {
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kvm_inject_undefined(vcpu);
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return false;
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}
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