Merge tag 'mtd/for-5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux
Pull MTD updates from Richard Weinberger: "NAND core changes: - Drop useless 'depends on' in Kconfig - Add an extra level in the Kconfig hierarchy - Trivial spellings - Dynamic allocation of the interface configurations - Dropping the default ONFI timing mode - Various cleanup (types, structures, naming, comments) - Hide the chip->data_interface indirection - Add the generic rb-gpios property - Add the ->choose_interface_config() hook - Introduce nand_choose_best_sdr_timings() - Use default values for tPROG_max and tBERS_max - Avoid redefining tR_max and tCCS_min - Add a helper to find the closest ONFI mode - bcm63xx MTD parsers: simplify CFE detection Raw NAND controller drivers changes: - fsl-upm: Deprecation of specific DT properties - fsl_upm: Driver rework and cleanup in favor of ->exec_op() - Ingenic: Cleanup ARRAY_SIZE() vs sizeof() use - brcmnand: ECC error handling on EDU transfers - brcmnand: Don't default to EDU transfers - qcom: Set BAM mode only if not set already - qcom: Avoid write to unavailable register - gpio: Driver rework in favor of ->exec_op() - tango: ->exec_op() conversion - mtk: ->exec_op() conversion Raw NAND chip drivers changes: - toshiba: Implement ->choose_interface_config() for TH58NVG2S3HBAI4 - toshiba: Implement ->choose_interface_config() for TC58NVG0S3E - toshiba: Implement ->choose_interface_config() for TC58TEG5DCLTA00 - hynix: Implement ->choose_interface_config() for H27UCG8T2ATR-BC HyperBus changes: - DMA support for TI's AM654 HyperBus controller driver. - HyperBus frontend driver for Renesas RPC-IF driver. SPI NOR core changes: - Support for Winbond w25q64jwm flash - Enable 4K sector support for mx25l12805d SPI NOR controller drivers changes: - intel-spi Add Alder Lake-S PCI ID MTD Core changes: - mtdoops: Don't run panic write twice - mtdconcat: Correctly handle panic write - Use DEFINE_SHOW_ATTRIBUTE" * tag 'mtd/for-5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (76 commits) mtd: hyperbus: Fix build failure when only RPCIF_HYPERBUS is enabled mtd: hyperbus: add Renesas RPC-IF driver Revert "mtd: spi-nor: Prefer asynchronous probe" mtd: parsers: bcm63xx: Do not make it modular mtd: spear_smi: Enable compile testing mtd: maps: vmu-flash: fix typos for struct memcard mtd: physmap: Add Baikal-T1 physically mapped ROM support mtd: maps: vmu-flash: simplify the return expression of probe_maple_vmu mtd: onenand: simplify the return expression of onenand_transfer_auto_oob mtd: rawnand: cadence: remove a redundant dev_err call mtd: rawnand: ams-delta: Fix non-OF build warning mtd: rawnand: Don't overwrite the error code from nand_set_ecc_soft_ops() mtd: rawnand: Introduce nand_set_ecc_on_host_ops() mtd: rawnand: atmel: Check return values for nand_read_data_op mtd: rawnand: vf610: Remove unused function vf610_nfc_transfer_size() mtd: rawnand: qcom: Simplify with dev_err_probe() mtd: rawnand: marvell: Fix and update kerneldoc mtd: rawnand: marvell: Simplify with dev_err_probe() mtd: rawnand: gpmi: Simplify with dev_err_probe() mtd: rawnand: atmel: Simplify with dev_err_probe() ...
This commit is contained in:
@@ -306,7 +306,7 @@ static struct davinci_nand_pdata da830_evm_nand_pdata = {
|
||||
.core_chipsel = 1,
|
||||
.parts = da830_evm_nand_partitions,
|
||||
.nr_parts = ARRAY_SIZE(da830_evm_nand_partitions),
|
||||
.ecc_mode = NAND_ECC_HW,
|
||||
.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST,
|
||||
.ecc_bits = 4,
|
||||
.bbt_options = NAND_BBT_USE_FLASH,
|
||||
.bbt_td = &da830_evm_nand_bbt_main_descr,
|
||||
|
||||
@@ -239,7 +239,7 @@ static struct davinci_nand_pdata da850_evm_nandflash_data = {
|
||||
.core_chipsel = 1,
|
||||
.parts = da850_evm_nandflash_partition,
|
||||
.nr_parts = ARRAY_SIZE(da850_evm_nandflash_partition),
|
||||
.ecc_mode = NAND_ECC_HW,
|
||||
.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST,
|
||||
.ecc_bits = 4,
|
||||
.bbt_options = NAND_BBT_USE_FLASH,
|
||||
.timing = &da850_evm_nandflash_timing,
|
||||
|
||||
@@ -82,7 +82,7 @@ static struct davinci_nand_pdata davinci_nand_data = {
|
||||
.mask_chipsel = BIT(14),
|
||||
.parts = davinci_nand_partitions,
|
||||
.nr_parts = ARRAY_SIZE(davinci_nand_partitions),
|
||||
.ecc_mode = NAND_ECC_HW,
|
||||
.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST,
|
||||
.bbt_options = NAND_BBT_USE_FLASH,
|
||||
.ecc_bits = 4,
|
||||
};
|
||||
|
||||
@@ -76,7 +76,8 @@ static struct davinci_nand_pdata davinci_nand_data = {
|
||||
.mask_chipsel = BIT(14),
|
||||
.parts = davinci_nand_partitions,
|
||||
.nr_parts = ARRAY_SIZE(davinci_nand_partitions),
|
||||
.ecc_mode = NAND_ECC_HW_SYNDROME,
|
||||
.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST,
|
||||
.ecc_placement = NAND_ECC_PLACEMENT_INTERLEAVED,
|
||||
.ecc_bits = 4,
|
||||
.bbt_options = NAND_BBT_USE_FLASH,
|
||||
};
|
||||
|
||||
@@ -146,7 +146,7 @@ static struct davinci_nand_pdata davinci_nand_data = {
|
||||
.mask_chipsel = BIT(14),
|
||||
.parts = davinci_nand_partitions,
|
||||
.nr_parts = ARRAY_SIZE(davinci_nand_partitions),
|
||||
.ecc_mode = NAND_ECC_HW,
|
||||
.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST,
|
||||
.bbt_options = NAND_BBT_USE_FLASH,
|
||||
.ecc_bits = 4,
|
||||
};
|
||||
|
||||
@@ -162,7 +162,7 @@ static struct davinci_nand_pdata davinci_evm_nandflash_data = {
|
||||
.core_chipsel = 0,
|
||||
.parts = davinci_evm_nandflash_partition,
|
||||
.nr_parts = ARRAY_SIZE(davinci_evm_nandflash_partition),
|
||||
.ecc_mode = NAND_ECC_HW,
|
||||
.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST,
|
||||
.ecc_bits = 1,
|
||||
.bbt_options = NAND_BBT_USE_FLASH,
|
||||
.timing = &davinci_evm_nandflash_timing,
|
||||
|
||||
@@ -91,7 +91,7 @@ static struct davinci_nand_pdata davinci_nand_data = {
|
||||
.mask_ale = 0x40000,
|
||||
.parts = davinci_nand_partitions,
|
||||
.nr_parts = ARRAY_SIZE(davinci_nand_partitions),
|
||||
.ecc_mode = NAND_ECC_HW,
|
||||
.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST,
|
||||
.ecc_bits = 1,
|
||||
.options = 0,
|
||||
};
|
||||
|
||||
@@ -432,7 +432,7 @@ static struct davinci_nand_pdata mityomapl138_nandflash_data = {
|
||||
.core_chipsel = 1,
|
||||
.parts = mityomapl138_nandflash_partition,
|
||||
.nr_parts = ARRAY_SIZE(mityomapl138_nandflash_partition),
|
||||
.ecc_mode = NAND_ECC_HW,
|
||||
.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST,
|
||||
.bbt_options = NAND_BBT_USE_FLASH,
|
||||
.options = NAND_BUSWIDTH_16,
|
||||
.ecc_bits = 1, /* 4 bit mode is not supported with 16 bit NAND */
|
||||
|
||||
@@ -90,7 +90,7 @@ static struct davinci_nand_pdata davinci_ntosd2_nandflash_data = {
|
||||
.core_chipsel = 0,
|
||||
.parts = davinci_ntosd2_nandflash_partition,
|
||||
.nr_parts = ARRAY_SIZE(davinci_ntosd2_nandflash_partition),
|
||||
.ecc_mode = NAND_ECC_HW,
|
||||
.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST,
|
||||
.ecc_bits = 1,
|
||||
.bbt_options = NAND_BBT_USE_FLASH,
|
||||
};
|
||||
|
||||
@@ -206,7 +206,7 @@ static struct davinci_nand_pdata omapl138_hawk_nandflash_data = {
|
||||
.core_chipsel = 1,
|
||||
.parts = omapl138_hawk_nandflash_partition,
|
||||
.nr_parts = ARRAY_SIZE(omapl138_hawk_nandflash_partition),
|
||||
.ecc_mode = NAND_ECC_HW,
|
||||
.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST,
|
||||
.ecc_bits = 4,
|
||||
.bbt_options = NAND_BBT_USE_FLASH,
|
||||
.options = NAND_BUSWIDTH_16,
|
||||
|
||||
@@ -191,7 +191,7 @@ static struct s3c2410_platform_nand smdk_nand_info = {
|
||||
.twrph1 = 20,
|
||||
.nr_sets = ARRAY_SIZE(smdk_nand_sets),
|
||||
.sets = smdk_nand_sets,
|
||||
.ecc_mode = NAND_ECC_SOFT,
|
||||
.engine_type = NAND_ECC_ENGINE_TYPE_SOFT,
|
||||
};
|
||||
|
||||
/* devices we initialise */
|
||||
|
||||
@@ -218,7 +218,7 @@ static struct s3c2410_platform_nand __initdata anubis_nand_info = {
|
||||
.nr_sets = ARRAY_SIZE(anubis_nand_sets),
|
||||
.sets = anubis_nand_sets,
|
||||
.select_chip = anubis_nand_select,
|
||||
.ecc_mode = NAND_ECC_SOFT,
|
||||
.engine_type = NAND_ECC_ENGINE_TYPE_SOFT,
|
||||
};
|
||||
|
||||
/* IDE channels */
|
||||
|
||||
@@ -109,7 +109,7 @@ static struct s3c2410_platform_nand __initdata at2440evb_nand_info = {
|
||||
.twrph1 = 40,
|
||||
.nr_sets = ARRAY_SIZE(at2440evb_nand_sets),
|
||||
.sets = at2440evb_nand_sets,
|
||||
.ecc_mode = NAND_ECC_SOFT,
|
||||
.engine_type = NAND_ECC_ENGINE_TYPE_SOFT,
|
||||
};
|
||||
|
||||
/* DM9000AEP 10/100 ethernet controller */
|
||||
|
||||
@@ -294,7 +294,7 @@ static struct s3c2410_platform_nand __initdata bast_nand_info = {
|
||||
.nr_sets = ARRAY_SIZE(bast_nand_sets),
|
||||
.sets = bast_nand_sets,
|
||||
.select_chip = bast_nand_select,
|
||||
.ecc_mode = NAND_ECC_SOFT,
|
||||
.engine_type = NAND_ECC_ENGINE_TYPE_SOFT,
|
||||
};
|
||||
|
||||
/* DM9000 */
|
||||
|
||||
@@ -417,7 +417,7 @@ static struct s3c2410_platform_nand __initdata gta02_nand_info = {
|
||||
.twrph1 = 15,
|
||||
.nr_sets = ARRAY_SIZE(gta02_nand_sets),
|
||||
.sets = gta02_nand_sets,
|
||||
.ecc_mode = NAND_ECC_SOFT,
|
||||
.engine_type = NAND_ECC_ENGINE_TYPE_SOFT,
|
||||
};
|
||||
|
||||
|
||||
|
||||
@@ -228,7 +228,7 @@ static struct s3c2410_platform_nand __initdata jive_nand_info = {
|
||||
.twrph1 = 40,
|
||||
.sets = jive_nand_sets,
|
||||
.nr_sets = ARRAY_SIZE(jive_nand_sets),
|
||||
.ecc_mode = NAND_ECC_SOFT,
|
||||
.engine_type = NAND_ECC_ENGINE_TYPE_SOFT,
|
||||
};
|
||||
|
||||
static int __init jive_mtdset(char *options)
|
||||
|
||||
@@ -296,7 +296,7 @@ static struct s3c2410_platform_nand mini2440_nand_info __initdata = {
|
||||
.nr_sets = ARRAY_SIZE(mini2440_nand_sets),
|
||||
.sets = mini2440_nand_sets,
|
||||
.ignore_unset_ecc = 1,
|
||||
.ecc_mode = NAND_ECC_HW,
|
||||
.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST,
|
||||
};
|
||||
|
||||
/* DM9000AEP 10/100 ethernet controller */
|
||||
|
||||
@@ -234,7 +234,7 @@ static struct s3c2410_platform_nand __initdata osiris_nand_info = {
|
||||
.nr_sets = ARRAY_SIZE(osiris_nand_sets),
|
||||
.sets = osiris_nand_sets,
|
||||
.select_chip = osiris_nand_select,
|
||||
.ecc_mode = NAND_ECC_SOFT,
|
||||
.engine_type = NAND_ECC_ENGINE_TYPE_SOFT,
|
||||
};
|
||||
|
||||
/* PCMCIA control and configuration */
|
||||
|
||||
@@ -287,7 +287,7 @@ static struct s3c2410_platform_nand __initdata qt2410_nand_info = {
|
||||
.twrph1 = 20,
|
||||
.nr_sets = ARRAY_SIZE(qt2410_nand_sets),
|
||||
.sets = qt2410_nand_sets,
|
||||
.ecc_mode = NAND_ECC_SOFT,
|
||||
.engine_type = NAND_ECC_ENGINE_TYPE_SOFT,
|
||||
};
|
||||
|
||||
/* UDC */
|
||||
|
||||
@@ -620,7 +620,7 @@ static struct s3c2410_platform_nand rx1950_nand_info = {
|
||||
.twrph1 = 15,
|
||||
.nr_sets = ARRAY_SIZE(rx1950_nand_sets),
|
||||
.sets = rx1950_nand_sets,
|
||||
.ecc_mode = NAND_ECC_SOFT,
|
||||
.engine_type = NAND_ECC_ENGINE_TYPE_SOFT,
|
||||
};
|
||||
|
||||
static struct s3c2410_udc_mach_info rx1950_udc_cfg __initdata = {
|
||||
|
||||
@@ -158,7 +158,7 @@ static struct s3c2410_platform_nand __initdata rx3715_nand_info = {
|
||||
.twrph1 = 15,
|
||||
.nr_sets = ARRAY_SIZE(rx3715_nand_sets),
|
||||
.sets = rx3715_nand_sets,
|
||||
.ecc_mode = NAND_ECC_SOFT,
|
||||
.engine_type = NAND_ECC_ENGINE_TYPE_SOFT,
|
||||
};
|
||||
|
||||
static struct platform_device *rx3715_devices[] __initdata = {
|
||||
|
||||
@@ -112,7 +112,7 @@ static struct s3c2410_platform_nand __initdata vstms_nand_info = {
|
||||
.twrph1 = 20,
|
||||
.nr_sets = ARRAY_SIZE(vstms_nand_sets),
|
||||
.sets = vstms_nand_sets,
|
||||
.ecc_mode = NAND_ECC_SOFT,
|
||||
.engine_type = NAND_ECC_ENGINE_TYPE_SOFT,
|
||||
};
|
||||
|
||||
static struct platform_device *vstms_devices[] __initdata = {
|
||||
|
||||
@@ -199,7 +199,7 @@ static struct s3c2410_platform_nand hmt_nand_info = {
|
||||
.twrph1 = 40,
|
||||
.nr_sets = ARRAY_SIZE(hmt_nand_sets),
|
||||
.sets = hmt_nand_sets,
|
||||
.ecc_mode = NAND_ECC_SOFT,
|
||||
.engine_type = NAND_ECC_ENGINE_TYPE_SOFT,
|
||||
};
|
||||
|
||||
static struct gpio_led hmt_leds[] = {
|
||||
|
||||
@@ -136,7 +136,7 @@ static struct s3c2410_platform_nand mini6410_nand_info = {
|
||||
.twrph1 = 40,
|
||||
.nr_sets = ARRAY_SIZE(mini6410_nand_sets),
|
||||
.sets = mini6410_nand_sets,
|
||||
.ecc_mode = NAND_ECC_SOFT,
|
||||
.engine_type = NAND_ECC_ENGINE_TYPE_SOFT,
|
||||
};
|
||||
|
||||
static struct s3c_fb_pd_win mini6410_lcd_type0_fb_win = {
|
||||
|
||||
@@ -188,7 +188,7 @@ static struct s3c2410_platform_nand real6410_nand_info = {
|
||||
.twrph1 = 40,
|
||||
.nr_sets = ARRAY_SIZE(real6410_nand_sets),
|
||||
.sets = real6410_nand_sets,
|
||||
.ecc_mode = NAND_ECC_SOFT,
|
||||
.engine_type = NAND_ECC_ENGINE_TYPE_SOFT,
|
||||
};
|
||||
|
||||
static struct platform_device *real6410_devices[] __initdata = {
|
||||
|
||||
Reference in New Issue
Block a user