forked from Minki/linux
iwlwifi: cleanup set_pwr_src
This patch cleans up semantic of set_pwr_src set_pwr_src is now part of apm handlers group in iwlcore Signed-off-by: Tomas Winkler <tomas.winkler@intel.com> Signed-off-by: Reinette Chatre <reinette.chatre@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -492,7 +492,7 @@ int iwl4965_hw_rxq_stop(struct iwl_priv *priv)
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return 0;
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}
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static int iwl4965_nic_set_pwr_src(struct iwl_priv *priv, int pwr_max)
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static int iwl4965_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
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{
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int ret;
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unsigned long flags;
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@ -504,20 +504,21 @@ static int iwl4965_nic_set_pwr_src(struct iwl_priv *priv, int pwr_max)
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return ret;
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}
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if (!pwr_max) {
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if (src == IWL_PWR_SRC_VAUX) {
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u32 val;
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ret = pci_read_config_dword(priv->pci_dev, PCI_POWER_SOURCE,
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&val);
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&val);
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if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT)
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if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) {
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iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
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APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
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~APMG_PS_CTRL_MSK_PWR_SRC);
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} else
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APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
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~APMG_PS_CTRL_MSK_PWR_SRC);
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}
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} else {
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iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
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APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
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~APMG_PS_CTRL_MSK_PWR_SRC);
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APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
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~APMG_PS_CTRL_MSK_PWR_SRC);
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}
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iwl_release_nic_access(priv);
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spin_unlock_irqrestore(&priv->lock, flags);
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@ -747,7 +748,8 @@ int iwl4965_hw_nic_init(struct iwl_priv *priv)
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IWL_DEBUG_INFO("HW Revision ID = 0x%X\n", rev_id);
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iwl4965_nic_set_pwr_src(priv, 1);
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rc = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
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spin_lock_irqsave(&priv->lock, flags);
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if ((rev_id & 0x80) == 0x80 && (rev_id & 0x7f) < 8) {
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@ -4272,6 +4274,9 @@ static struct iwl_lib_ops iwl4965_lib = {
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.is_valid_rtc_data_addr = iwl4965_hw_valid_rtc_data_addr,
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.alive_notify = iwl4965_alive_notify,
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.load_ucode = iwl4965_load_bsm,
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.apm_ops = {
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.set_pwr_src = iwl4965_set_pwr_src,
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},
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.eeprom_ops = {
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.verify_signature = iwlcore_eeprom_verify_signature,
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.acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
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@ -252,6 +252,11 @@ struct iwl4965_clip_group {
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/* Power management (not Tx power) structures */
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enum iwl_pwr_src {
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IWL_PWR_SRC_VMAIN,
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IWL_PWR_SRC_VAUX,
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};
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struct iwl4965_power_vec_entry {
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struct iwl4965_powertable_cmd cmd;
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u8 no_dtim;
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@ -115,6 +115,9 @@ struct iwl_lib_ops {
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int (*load_ucode)(struct iwl_priv *priv);
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/* rfkill */
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void (*radio_kill_sw)(struct iwl_priv *priv, int disable_radio);
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struct {
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int (*set_pwr_src)(struct iwl_priv *priv, enum iwl_pwr_src src);
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} apm_ops;
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/* eeprom operations (as defined in iwl-eeprom.h) */
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struct iwl_eeprom_ops eeprom_ops;
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};
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@ -170,6 +170,10 @@
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#define CSR49_FH_INT_TX_MASK (CSR_FH_INT_BIT_TX_CHNL1 | \
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CSR_FH_INT_BIT_TX_CHNL0)
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/* GPIO */
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#define CSR_GPIO_IN_BIT_AUX_POWER (0x00000200)
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#define CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000)
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#define CSR_GPIO_IN_VAL_VMAIN_PWR_SRC (0x00000200)
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/* RESET */
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#define CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001)
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@ -206,11 +210,6 @@
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#define CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004)
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#define CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008)
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/* GPIO */
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#define CSR_GPIO_IN_BIT_AUX_POWER (0x00000200)
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#define CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000)
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#define CSR_GPIO_IN_VAL_VMAIN_PWR_SRC CSR_GPIO_IN_BIT_AUX_POWER
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/* GI Chicken Bits */
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#define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000)
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#define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000)
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