leandrof/linux
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mt76x0: correct RF access via RF_CSR register.

Browse Source 
PCIe version don't use MCU for RF registers access. We need
to correct RF CSR method to support up to 127 RF registers.

Signed-off-by: Stanislaw Gruszka <sgruszka@redhat.com>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
This commit is contained in:
Stanislaw Gruszka 2018-10-04 12:04:52 +02:00 committed by Felix Fietkau
parent bed259051d
commit 6f223a3dab
2 changed files with 4 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/net/wireless/mediatek/mt76/mt76x0/phy.c
View File

@ -37,7 +37,7 @@ mt76x0_rf_csr_wr(struct mt76x02_dev *dev, u32 offset, u8 value)
bank = MT_RF_BANK(offset);
reg = MT_RF_REG(offset);
if (WARN_ON_ONCE(reg > 64) || WARN_ON_ONCE(bank) > 8)
if (WARN_ON_ONCE(reg > 127) || WARN_ON_ONCE(bank) > 8)
return -EINVAL;
mutex_lock(&dev->phy_mutex);
@ -76,7 +76,7 @@ static int mt76x0_rf_csr_rr(struct mt76x02_dev *dev, u32 offset)
bank = MT_RF_BANK(offset);
reg = MT_RF_REG(offset);
if (WARN_ON_ONCE(reg > 64) || WARN_ON_ONCE(bank) > 8)
if (WARN_ON_ONCE(reg > 127) || WARN_ON_ONCE(bank) > 8)
return -EINVAL;
mutex_lock(&dev->phy_mutex);
@ -119,7 +119,6 @@ rf_wr(struct mt76x02_dev *dev, u32 offset, u8 val)
return mt76_wr_rp(dev, MT_MCU_MEMMAP_RF, &pair, 1);
} else {
WARN_ON_ONCE(1);
return mt76x0_rf_csr_wr(dev, offset, val);
}
}
@ -138,7 +137,6 @@ rf_rr(struct mt76x02_dev *dev, u32 offset)
ret = mt76_rd_rp(dev, MT_MCU_MEMMAP_RF, &pair, 1);
val = pair.value;
} else {
WARN_ON_ONCE(1);
ret = val = mt76x0_rf_csr_rr(dev, offset);
}

4
drivers/net/wireless/mediatek/mt76/mt76x02_regs.h
View File

@ -205,8 +205,8 @@
#define MT_TXQ_STA 0x0434
#define MT_RF_CSR_CFG 0x0500
#define MT_RF_CSR_CFG_DATA GENMASK(7, 0)
#define MT_RF_CSR_CFG_REG_ID GENMASK(13, 8)
#define MT_RF_CSR_CFG_REG_BANK GENMASK(17, 14)
#define MT_RF_CSR_CFG_REG_ID GENMASK(14, 8)
#define MT_RF_CSR_CFG_REG_BANK GENMASK(17, 15)
#define MT_RF_CSR_CFG_WR BIT(30)
#define MT_RF_CSR_CFG_KICK BIT(31)