forked from Minki/linux
drm/i915: make raw access function work on uncore
This allows us to ditch i915 in some more places. v2: use local var in check_vgpu (Paulo) Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20190319183543.13679-9-daniele.ceraolospurio@intel.com
This commit is contained in:
Daniele Ceraolo Spurio
Chris Wilson
parent
25286aaca9
commit
6ebc9692a7
@ -3484,17 +3484,17 @@ static inline u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
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#define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
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#define __raw_read(x, s) \
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static inline uint##x##_t __raw_i915_read##x(const struct drm_i915_private *dev_priv, \
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static inline uint##x##_t __raw_i915_read##x(const struct intel_uncore *uncore, \
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i915_reg_t reg) \
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{ \
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return read##s(dev_priv->uncore.regs + i915_mmio_reg_offset(reg)); \
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return read##s(uncore->regs + i915_mmio_reg_offset(reg)); \
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}
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#define __raw_write(x, s) \
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static inline void __raw_i915_write##x(const struct drm_i915_private *dev_priv, \
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static inline void __raw_i915_write##x(const struct intel_uncore *uncore, \
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i915_reg_t reg, uint##x##_t val) \
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{ \
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write##s(val, dev_priv->uncore.regs + i915_mmio_reg_offset(reg)); \
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write##s(val, uncore->regs + i915_mmio_reg_offset(reg)); \
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}
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__raw_read(8, b)
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__raw_read(16, w)
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@ -3535,9 +3535,9 @@ __raw_write(64, q)
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* therefore generally be serialised, by either the dev_priv->uncore.lock or
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* a more localised lock guarding all access to that bank of registers.
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*/
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#define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
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#define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
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#define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
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#define I915_READ_FW(reg__) __raw_i915_read32(&dev_priv->uncore, (reg__))
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#define I915_WRITE_FW(reg__, val__) __raw_i915_write32(&dev_priv->uncore, (reg__), (val__))
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#define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(&dev_priv->uncore, (reg__), (val__))
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#define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
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/* "Broadcast RGB" property */
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@ -60,22 +60,23 @@
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*/
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void i915_check_vgpu(struct drm_i915_private *dev_priv)
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{
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struct intel_uncore *uncore = &dev_priv->uncore;
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u64 magic;
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u16 version_major;
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BUILD_BUG_ON(sizeof(struct vgt_if) != VGT_PVINFO_SIZE);
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magic = __raw_i915_read64(dev_priv, vgtif_reg(magic));
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magic = __raw_i915_read64(uncore, vgtif_reg(magic));
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if (magic != VGT_MAGIC)
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return;
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version_major = __raw_i915_read16(dev_priv, vgtif_reg(version_major));
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version_major = __raw_i915_read16(uncore, vgtif_reg(version_major));
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if (version_major < VGT_VERSION_MAJOR) {
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DRM_INFO("VGT interface version mismatch!\n");
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return;
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}
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dev_priv->vgpu.caps = __raw_i915_read32(dev_priv, vgtif_reg(vgt_caps));
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dev_priv->vgpu.caps = __raw_i915_read32(uncore, vgtif_reg(vgt_caps));
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dev_priv->vgpu.active = true;
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DRM_INFO("Virtual GPU for Intel GVT-g detected.\n");
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@ -31,7 +31,7 @@
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#define FORCEWAKE_ACK_TIMEOUT_MS 50
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#define GT_FIFO_TIMEOUT_MS 10
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#define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32((dev_priv__), (reg__))
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#define __raw_posting_read(uncore__, reg__) (void)__raw_i915_read32((uncore__), (reg__))
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static const char * const forcewake_domain_names[] = {
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"render",
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@ -275,23 +275,23 @@ fw_domains_reset(struct intel_uncore *uncore,
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fw_domain_reset(d);
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}
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static inline u32 gt_thread_status(struct drm_i915_private *dev_priv)
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static inline u32 gt_thread_status(struct intel_uncore *uncore)
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{
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u32 val;
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val = __raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG);
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val = __raw_i915_read32(uncore, GEN6_GT_THREAD_STATUS_REG);
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val &= GEN6_GT_THREAD_STATUS_CORE_MASK;
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return val;
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}
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static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
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static void __gen6_gt_wait_for_thread_c0(struct intel_uncore *uncore)
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{
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/*
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* w/a for a sporadic read returning 0 by waiting for the GT
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* thread to wake up.
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*/
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WARN_ONCE(wait_for_atomic_us(gt_thread_status(dev_priv) == 0, 5000),
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WARN_ONCE(wait_for_atomic_us(gt_thread_status(uncore) == 0, 5000),
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"GT thread status wait timed out\n");
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}
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@ -301,30 +301,29 @@ static void fw_domains_get_with_thread_status(struct intel_uncore *uncore,
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fw_domains_get(uncore, fw_domains);
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/* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */
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__gen6_gt_wait_for_thread_c0(uncore_to_i915(uncore));
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__gen6_gt_wait_for_thread_c0(uncore);
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}
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static inline u32 fifo_free_entries(struct drm_i915_private *dev_priv)
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static inline u32 fifo_free_entries(struct intel_uncore *uncore)
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{
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u32 count = __raw_i915_read32(dev_priv, GTFIFOCTL);
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u32 count = __raw_i915_read32(uncore, GTFIFOCTL);
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return count & GT_FIFO_FREE_ENTRIES_MASK;
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}
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static void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
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static void __gen6_gt_wait_for_fifo(struct intel_uncore *uncore)
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{
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struct intel_uncore *uncore = &dev_priv->uncore;
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u32 n;
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/* On VLV, FIFO will be shared by both SW and HW.
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* So, we need to read the FREE_ENTRIES everytime */
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if (IS_VALLEYVIEW(dev_priv))
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n = fifo_free_entries(dev_priv);
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if (IS_VALLEYVIEW(uncore_to_i915(uncore)))
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n = fifo_free_entries(uncore);
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else
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n = uncore->fifo_count;
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if (n <= GT_FIFO_NUM_RESERVED_ENTRIES) {
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if (wait_for_atomic((n = fifo_free_entries(dev_priv)) >
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if (wait_for_atomic((n = fifo_free_entries(uncore)) >
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GT_FIFO_NUM_RESERVED_ENTRIES,
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GT_FIFO_TIMEOUT_MS)) {
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DRM_DEBUG("GT_FIFO timeout, entries: %u\n", n);
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@ -452,7 +451,7 @@ static void intel_uncore_edram_detect(struct drm_i915_private *dev_priv)
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if (IS_HASWELL(dev_priv) ||
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IS_BROADWELL(dev_priv) ||
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INTEL_GEN(dev_priv) >= 9) {
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dev_priv->edram_cap = __raw_i915_read32(dev_priv,
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dev_priv->edram_cap = __raw_i915_read32(&dev_priv->uncore,
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HSW_EDRAM_CAP);
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/* NB: We can't write IDICR yet because we do not have gt funcs
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@ -467,43 +466,43 @@ static void intel_uncore_edram_detect(struct drm_i915_private *dev_priv)
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}
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static bool
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fpga_check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
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fpga_check_for_unclaimed_mmio(struct intel_uncore *uncore)
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{
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u32 dbg;
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dbg = __raw_i915_read32(dev_priv, FPGA_DBG);
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dbg = __raw_i915_read32(uncore, FPGA_DBG);
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if (likely(!(dbg & FPGA_DBG_RM_NOCLAIM)))
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return false;
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__raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
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__raw_i915_write32(uncore, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
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return true;
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}
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static bool
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vlv_check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
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vlv_check_for_unclaimed_mmio(struct intel_uncore *uncore)
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{
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u32 cer;
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cer = __raw_i915_read32(dev_priv, CLAIM_ER);
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cer = __raw_i915_read32(uncore, CLAIM_ER);
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if (likely(!(cer & (CLAIM_ER_OVERFLOW | CLAIM_ER_CTR_MASK))))
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return false;
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__raw_i915_write32(dev_priv, CLAIM_ER, CLAIM_ER_CLR);
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__raw_i915_write32(uncore, CLAIM_ER, CLAIM_ER_CLR);
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return true;
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}
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static bool
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gen6_check_for_fifo_debug(struct drm_i915_private *dev_priv)
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gen6_check_for_fifo_debug(struct intel_uncore *uncore)
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{
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u32 fifodbg;
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fifodbg = __raw_i915_read32(dev_priv, GTFIFODBG);
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fifodbg = __raw_i915_read32(uncore, GTFIFODBG);
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if (unlikely(fifodbg)) {
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DRM_DEBUG_DRIVER("GTFIFODBG = 0x08%x\n", fifodbg);
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__raw_i915_write32(dev_priv, GTFIFODBG, fifodbg);
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__raw_i915_write32(uncore, GTFIFODBG, fifodbg);
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}
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return fifodbg;
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@ -512,16 +511,17 @@ gen6_check_for_fifo_debug(struct drm_i915_private *dev_priv)
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static bool
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check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
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{
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struct intel_uncore *uncore = &dev_priv->uncore;
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bool ret = false;
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if (HAS_FPGA_DBG_UNCLAIMED(dev_priv))
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ret |= fpga_check_for_unclaimed_mmio(dev_priv);
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ret |= fpga_check_for_unclaimed_mmio(uncore);
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if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
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ret |= vlv_check_for_unclaimed_mmio(dev_priv);
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ret |= vlv_check_for_unclaimed_mmio(uncore);
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if (IS_GEN_RANGE(dev_priv, 6, 7))
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ret |= gen6_check_for_fifo_debug(dev_priv);
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ret |= gen6_check_for_fifo_debug(uncore);
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return ret;
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}
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@ -537,8 +537,8 @@ static void __intel_uncore_early_sanitize(struct intel_uncore *uncore,
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/* WaDisableShadowRegForCpd:chv */
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if (IS_CHERRYVIEW(i915)) {
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__raw_i915_write32(i915, GTFIFOCTL,
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__raw_i915_read32(i915, GTFIFOCTL) |
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__raw_i915_write32(uncore, GTFIFOCTL,
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__raw_i915_read32(uncore, GTFIFOCTL) |
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GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
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GT_FIFO_CTL_RC6_POLICY_STALL);
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}
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@ -550,7 +550,7 @@ static void __intel_uncore_early_sanitize(struct intel_uncore *uncore,
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uncore->funcs.force_wake_get(uncore, restore_forcewake);
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if (IS_GEN_RANGE(i915, 6, 7))
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uncore->fifo_count = fifo_free_entries(i915);
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uncore->fifo_count = fifo_free_entries(uncore);
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spin_unlock_irq(&uncore->lock);
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}
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iosf_mbi_punit_release();
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@ -1063,12 +1063,12 @@ static const struct intel_forcewake_range __gen11_fw_ranges[] = {
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};
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static void
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ilk_dummy_write(struct drm_i915_private *dev_priv)
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ilk_dummy_write(struct intel_uncore *uncore)
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{
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/* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
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* the chip from rc6 before touching it for real. MI_MODE is masked,
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* hence harmless to write 0 into. */
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__raw_i915_write32(dev_priv, MI_MODE, 0);
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__raw_i915_write32(uncore, MI_MODE, 0);
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}
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static void
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@ -1098,6 +1098,7 @@ unclaimed_reg_debug(struct drm_i915_private *dev_priv,
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}
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#define GEN2_READ_HEADER(x) \
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struct intel_uncore *uncore = &dev_priv->uncore; \
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u##x val = 0; \
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assert_rpm_wakelock_held(dev_priv);
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@ -1109,7 +1110,7 @@ unclaimed_reg_debug(struct drm_i915_private *dev_priv,
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static u##x \
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gen2_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
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GEN2_READ_HEADER(x); \
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val = __raw_i915_read##x(dev_priv, reg); \
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val = __raw_i915_read##x(uncore, reg); \
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GEN2_READ_FOOTER; \
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}
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@ -1117,8 +1118,8 @@ gen2_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
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static u##x \
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gen5_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
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GEN2_READ_HEADER(x); \
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ilk_dummy_write(dev_priv); \
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val = __raw_i915_read##x(dev_priv, reg); \
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ilk_dummy_write(uncore); \
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val = __raw_i915_read##x(uncore, reg); \
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GEN2_READ_FOOTER; \
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}
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@ -1188,7 +1189,7 @@ func##_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) {
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fw_engine = __##func##_reg_read_fw_domains(uncore, offset); \
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if (fw_engine) \
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__force_wake_auto(uncore, fw_engine); \
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val = __raw_i915_read##x(dev_priv, reg); \
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val = __raw_i915_read##x(uncore, reg); \
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GEN6_READ_FOOTER; \
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}
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#define __gen6_read(x) __gen_read(gen6, x)
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@ -1215,6 +1216,7 @@ __gen6_read(64)
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#undef GEN6_READ_HEADER
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#define GEN2_WRITE_HEADER \
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struct intel_uncore *uncore = &dev_priv->uncore; \
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trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
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assert_rpm_wakelock_held(dev_priv); \
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@ -1224,7 +1226,7 @@ __gen6_read(64)
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static void \
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gen2_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
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GEN2_WRITE_HEADER; \
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__raw_i915_write##x(dev_priv, reg, val); \
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__raw_i915_write##x(uncore, reg, val); \
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GEN2_WRITE_FOOTER; \
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}
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@ -1232,8 +1234,8 @@ gen2_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool
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static void \
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gen5_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
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GEN2_WRITE_HEADER; \
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ilk_dummy_write(dev_priv); \
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__raw_i915_write##x(dev_priv, reg, val); \
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ilk_dummy_write(uncore); \
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__raw_i915_write##x(uncore, reg, val); \
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GEN2_WRITE_FOOTER; \
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}
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@ -1268,8 +1270,8 @@ static void \
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gen6_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
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GEN6_WRITE_HEADER; \
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if (NEEDS_FORCE_WAKE(offset)) \
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__gen6_gt_wait_for_fifo(dev_priv); \
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__raw_i915_write##x(dev_priv, reg, val); \
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__gen6_gt_wait_for_fifo(uncore); \
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__raw_i915_write##x(uncore, reg, val); \
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GEN6_WRITE_FOOTER; \
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}
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@ -1281,7 +1283,7 @@ func##_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, boo
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fw_engine = __##func##_reg_write_fw_domains(uncore, offset); \
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if (fw_engine) \
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__force_wake_auto(uncore, fw_engine); \
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__raw_i915_write##x(dev_priv, reg, val); \
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__raw_i915_write##x(uncore, reg, val); \
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GEN6_WRITE_FOOTER; \
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}
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#define __gen8_write(x) __gen_write(gen8, x)
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@ -1468,15 +1470,15 @@ static void intel_uncore_fw_domains_init(struct intel_uncore *uncore)
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* before the ecobus check.
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*/
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__raw_i915_write32(i915, FORCEWAKE, 0);
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__raw_posting_read(i915, ECOBUS);
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__raw_i915_write32(uncore, FORCEWAKE, 0);
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__raw_posting_read(uncore, ECOBUS);
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fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
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FORCEWAKE_MT, FORCEWAKE_MT_ACK);
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spin_lock_irq(&uncore->lock);
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fw_domains_get_with_thread_status(uncore, FORCEWAKE_RENDER);
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ecobus = __raw_i915_read32(i915, ECOBUS);
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ecobus = __raw_i915_read32(uncore, ECOBUS);
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fw_domains_put(uncore, FORCEWAKE_RENDER);
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spin_unlock_irq(&uncore->lock);
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