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dt-bindings: arm: hisilicon: convert LPC controller bindings to json-schema

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Convert the Hisilicon Hip06 SoCs implement a Low Pin Count (LPC)
controller binding to DT schema format using json-schema.

Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
Link: https://lore.kernel.org/r/20200929141454.2312-18-thunder.leizhen@huawei.com
Signed-off-by: Rob Herring <robh@kernel.org>
This commit is contained in:
Zhen Lei 2020-09-29 22:14:54 +08:00 committed by Rob Herring
parent 9266ff505a
commit 6db13e108e
2 changed files with 61 additions and 33 deletions
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33
Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt
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@ -1,33 +0,0 @@
Hisilicon Hip06 Low Pin Count device
Hisilicon Hip06 SoCs implement a Low Pin Count (LPC) controller, which
provides I/O access to some legacy ISA devices.
Hip06 is based on arm64 architecture where there is no I/O space. So, the
I/O ports here are not CPU addresses, and there is no 'ranges' property in
LPC device node.
Required properties:
- compatible: value should be as follows:
(a) "hisilicon,hip06-lpc"
(b) "hisilicon,hip07-lpc"
- #address-cells: must be 2 which stick to the ISA/EISA binding doc.
- #size-cells: must be 1 which stick to the ISA/EISA binding doc.
- reg: base memory range where the LPC register set is mapped.
Note:
The node name before '@' must be "isa" to represent the binding stick to the
ISA/EISA binding specification.
Example:
isa@a01b0000 {
compatible = "hisilicon,hip06-lpc";
#address-cells = <2>;
#size-cells = <1>;
reg = <0x0 0xa01b0000 0x0 0x1000>;
ipmi0: bt@e4 {
compatible = "ipmi-bt";
device_type = "ipmi";
reg = <0x01 0xe4 0x04>;
};
};

61
Documentation/devicetree/bindings/arm/hisilicon/low-pin-count.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/hisilicon/low-pin-count.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Hisilicon HiP06 Low Pin Count device
maintainers:
- Wei Xu <xuwei5@hisilicon.com>
description: |
Hisilicon HiP06 SoCs implement a Low Pin Count (LPC) controller, which
provides I/O access to some legacy ISA devices.
HiP06 is based on arm64 architecture where there is no I/O space. So, the
I/O ports here are not CPU addresses, and there is no 'ranges' property in
LPC device node.
properties:
$nodename:
pattern: '^isa@[0-9a-f]+$'
description: |
The node name before '@' must be "isa" to represent the binding stick
to the ISA/EISA binding specification.
compatible:
enum:
- hisilicon,hip06-lpc
- hisilicon,hip07-lpc
reg:
maxItems: 1
'#address-cells':
const: 2
'#size-cells':
const: 1
required:
- compatible
- reg
additionalProperties:
type: object
examples:
- |
isa@a01b0000 {
compatible = "hisilicon,hip06-lpc";
#address-cells = <2>;
#size-cells = <1>;
reg = <0xa01b0000 0x1000>;
ipmi0: bt@e4 {
compatible = "ipmi-bt";
device_type = "ipmi";
reg = <0x01 0xe4 0x04>;
};
};
...