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drm/nouveau/disp/nv50-: simplify definition of cursor channels

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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2018-05-08 20:39:46 +10:00
parent 3ceeef9c03
commit 6d41a7536f
21 changed files with 51 additions and 249 deletions
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3
drivers/gpu/drm/nouveau/nvkm/engine/disp/Kbuild
View File

@ -100,10 +100,7 @@ nvkm-y += nvkm/engine/disp/piocnv50.o
nvkm-y += nvkm/engine/disp/piocgf119.o
nvkm-y += nvkm/engine/disp/cursnv50.o
nvkm-y += nvkm/engine/disp/cursg84.o
nvkm-y += nvkm/engine/disp/cursgt215.o
nvkm-y += nvkm/engine/disp/cursgf119.o
nvkm-y += nvkm/engine/disp/cursgk104.o
nvkm-y += nvkm/engine/disp/cursgp102.o
nvkm-y += nvkm/engine/disp/oimmnv50.o

43
drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.h
View File

@ -50,6 +50,10 @@ void nv50_disp_chan_uevent_send(struct nv50_disp *, int);
extern const struct nvkm_event_func gf119_disp_chan_uevent;
int nv50_disp_curs_new_(const struct nv50_disp_chan_func *,
struct nv50_disp *, int ctrl, int user,
const struct nvkm_oclass *, void *argv, u32 argc,
struct nvkm_object **);
int nv50_disp_oimm_new_(const struct nv50_disp_chan_func *,
struct nv50_disp *, int ctrl, int user,
const struct nvkm_oclass *, void *argv, u32 argc,
@ -65,6 +69,8 @@ int nv50_disp_ovly_new_(const struct nv50_disp_dmac_func *,
const struct nvkm_oclass *, void *argv, u32 argc,
struct nvkm_object **);
int nv50_disp_curs_new(const struct nvkm_oclass *, void *, u32,
struct nv50_disp *, struct nvkm_object **);
int nv50_disp_oimm_new(const struct nvkm_oclass *, void *, u32,
struct nv50_disp *, struct nvkm_object **);
int nv50_disp_base_new(const struct nvkm_oclass *, void *, u32,
@ -80,6 +86,8 @@ int g84_disp_ovly_new(const struct nvkm_oclass *, void *, u32,
int gt200_disp_ovly_new(const struct nvkm_oclass *, void *, u32,
struct nv50_disp *, struct nvkm_object **);
int gf119_disp_curs_new(const struct nvkm_oclass *, void *, u32,
struct nv50_disp *, struct nvkm_object **);
int gf119_disp_oimm_new(const struct nvkm_oclass *, void *, u32,
struct nv50_disp *, struct nvkm_object **);
int gf119_disp_base_new(const struct nvkm_oclass *, void *, u32,
@ -90,6 +98,8 @@ int gf119_disp_ovly_new(const struct nvkm_oclass *, void *, u32,
int gk104_disp_ovly_new(const struct nvkm_oclass *, void *, u32,
struct nv50_disp *, struct nvkm_object **);
int gp102_disp_curs_new(const struct nvkm_oclass *, void *, u32,
struct nv50_disp *, struct nvkm_object **);
int gp102_disp_oimm_new(const struct nvkm_oclass *, void *, u32,
struct nv50_disp *, struct nvkm_object **);
int gp102_disp_base_new(const struct nvkm_oclass *, void *, u32,
@ -139,37 +149,4 @@ extern const struct nv50_disp_chan_mthd gf119_disp_base_mthd;
extern const struct nv50_disp_chan_mthd gk104_disp_core_chan_mthd;
extern const struct nv50_disp_chan_mthd gk104_disp_ovly_mthd;
struct nv50_disp_pioc_oclass {
int (*ctor)(const struct nv50_disp_chan_func *,
const struct nv50_disp_chan_mthd *,
struct nv50_disp_root *, int ctrl, int user,
const struct nvkm_oclass *, void *data, u32 size,
struct nvkm_object **);
struct nvkm_sclass base;
const struct nv50_disp_chan_func *func;
const struct nv50_disp_chan_mthd *mthd;
struct {
int ctrl;
int user;
} chid;
};
extern const struct nv50_disp_pioc_oclass nv50_disp_curs_oclass;
extern const struct nv50_disp_pioc_oclass g84_disp_curs_oclass;
extern const struct nv50_disp_pioc_oclass gt215_disp_curs_oclass;
extern const struct nv50_disp_pioc_oclass gf119_disp_curs_oclass;
extern const struct nv50_disp_pioc_oclass gk104_disp_curs_oclass;
extern const struct nv50_disp_pioc_oclass gp102_disp_curs_oclass;
int nv50_disp_curs_new(const struct nv50_disp_chan_func *,
const struct nv50_disp_chan_mthd *,
struct nv50_disp_root *, int ctrl, int user,
const struct nvkm_oclass *, void *data, u32 size,
struct nvkm_object **);
#endif

37
drivers/gpu/drm/nouveau/nvkm/engine/disp/cursg84.c
View File

@ -1,37 +0,0 @@
/*
* Copyright 2015 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
#include "channv50.h"
#include "rootnv50.h"
#include <nvif/class.h>
const struct nv50_disp_pioc_oclass
g84_disp_curs_oclass = {
.base.oclass = G82_DISP_CURSOR,
.base.minver = 0,
.base.maxver = 0,
.ctor = nv50_disp_curs_new,
.func = &nv50_disp_pioc_func,
.chid = { 7, 7 },
};

19
drivers/gpu/drm/nouveau/nvkm/engine/disp/cursgf119.c
View File

@ -22,16 +22,11 @@
* Authors: Ben Skeggs
*/
#include "channv50.h"
#include "rootnv50.h"
#include <nvif/class.h>
const struct nv50_disp_pioc_oclass
gf119_disp_curs_oclass = {
.base.oclass = GF110_DISP_CURSOR,
.base.minver = 0,
.base.maxver = 0,
.ctor = nv50_disp_curs_new,
.func = &gf119_disp_pioc_func,
.chid = { 13, 13 },
};
int
gf119_disp_curs_new(const struct nvkm_oclass *oclass, void *argv, u32 argc,
struct nv50_disp *disp, struct nvkm_object **pobject)
{
return nv50_disp_curs_new_(&gf119_disp_pioc_func, disp, 13, 13,
oclass, argv, argc, pobject);
}

37
drivers/gpu/drm/nouveau/nvkm/engine/disp/cursgk104.c
View File

@ -1,37 +0,0 @@
/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "channv50.h"
#include "rootnv50.h"
#include <nvif/class.h>
const struct nv50_disp_pioc_oclass
gk104_disp_curs_oclass = {
.base.oclass = GK104_DISP_CURSOR,
.base.minver = 0,
.base.maxver = 0,
.ctor = nv50_disp_curs_new,
.func = &gf119_disp_pioc_func,
.chid = { 13, 13 },
};

19
drivers/gpu/drm/nouveau/nvkm/engine/disp/cursgp102.c
View File

@ -22,16 +22,11 @@
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
#include "channv50.h"
#include "rootnv50.h"
#include <nvif/class.h>
const struct nv50_disp_pioc_oclass
gp102_disp_curs_oclass = {
.base.oclass = GK104_DISP_CURSOR,
.base.minver = 0,
.base.maxver = 0,
.ctor = nv50_disp_curs_new,
.func = &gf119_disp_pioc_func,
.chid = { 13, 17 },
};
int
gp102_disp_curs_new(const struct nvkm_oclass *oclass, void *argv, u32 argc,
struct nv50_disp *disp, struct nvkm_object **pobject)
{
return nv50_disp_curs_new_(&gf119_disp_pioc_func, disp, 13, 17,
oclass, argv, argc, pobject);
}

37
drivers/gpu/drm/nouveau/nvkm/engine/disp/cursgt215.c
View File

@ -1,37 +0,0 @@
/*
* Copyright 2015 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
#include "channv50.h"
#include "rootnv50.h"
#include <nvif/class.h>
const struct nv50_disp_pioc_oclass
gt215_disp_curs_oclass = {
.base.oclass = GT214_DISP_CURSOR,
.base.minver = 0,
.base.maxver = 0,
.ctor = nv50_disp_curs_new,
.func = &nv50_disp_pioc_func,
.chid = { 7, 7 },
};

36
drivers/gpu/drm/nouveau/nvkm/engine/disp/cursnv50.c
View File

@ -23,30 +23,26 @@
*/
#include "channv50.h"
#include "head.h"
#include "rootnv50.h"
#include <core/client.h>
#include <nvif/class.h>
#include <nvif/cl507a.h>
#include <nvif/unpack.h>
int
nv50_disp_curs_new(const struct nv50_disp_chan_func *func,
const struct nv50_disp_chan_mthd *mthd,
struct nv50_disp_root *root, int ctrl, int user,
const struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
nv50_disp_curs_new_(const struct nv50_disp_chan_func *func,
struct nv50_disp *disp, int ctrl, int user,
const struct nvkm_oclass *oclass, void *argv, u32 argc,
struct nvkm_object **pobject)
{
union {
struct nv50_disp_cursor_v0 v0;
} *args = data;
} *args = argv;
struct nvkm_object *parent = oclass->parent;
struct nv50_disp *disp = root->disp;
int head, ret = -ENOSYS;
nvif_ioctl(parent, "create disp cursor size %d\n", size);
if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
nvif_ioctl(parent, "create disp cursor size %d\n", argc);
if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false))) {
nvif_ioctl(parent, "create disp cursor vers %d head %d\n",
args->v0.version, args->v0.head);
if (!nvkm_head_find(&disp->base, args->v0.head))
@ -55,16 +51,14 @@ nv50_disp_curs_new(const struct nv50_disp_chan_func *func,
} else
return ret;
return nv50_disp_chan_new_(func, mthd, disp, ctrl + head, user + head,
return nv50_disp_chan_new_(func, NULL, disp, ctrl + head, user + head,
head, oclass, pobject);
}
const struct nv50_disp_pioc_oclass
nv50_disp_curs_oclass = {
.base.oclass = NV50_DISP_CURSOR,
.base.minver = 0,
.base.maxver = 0,
.ctor = nv50_disp_curs_new,
.func = &nv50_disp_pioc_func,
.chid = { 7, 7 },
};
int
nv50_disp_curs_new(const struct nvkm_oclass *oclass, void *argv, u32 argc,
struct nv50_disp *disp, struct nvkm_object **pobject)
{
return nv50_disp_curs_new_(&nv50_disp_pioc_func, disp, 7, 7,
oclass, argv, argc, pobject);
}

4
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootg84.c
View File

@ -31,10 +31,8 @@ g84_disp_root = {
.dmac = {
&g84_disp_core_oclass,
},
.pioc = {
&g84_disp_curs_oclass,
},
.user = {
{{0,0,G82_DISP_CURSOR }, nv50_disp_curs_new },
{{0,0,G82_DISP_OVERLAY }, nv50_disp_oimm_new },
{{0,0,G82_DISP_BASE_CHANNEL_DMA }, g84_disp_base_new },
{{0,0,G82_DISP_OVERLAY_CHANNEL_DMA}, g84_disp_ovly_new },

4
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootg94.c
View File

@ -31,10 +31,8 @@ g94_disp_root = {
.dmac = {
&g94_disp_core_oclass,
},
.pioc = {
&g84_disp_curs_oclass,
},
.user = {
{{0,0, G82_DISP_CURSOR }, nv50_disp_curs_new },
{{0,0, G82_DISP_OVERLAY }, nv50_disp_oimm_new },
{{0,0,GT200_DISP_BASE_CHANNEL_DMA }, g84_disp_base_new },
{{0,0,GT200_DISP_OVERLAY_CHANNEL_DMA}, gt200_disp_ovly_new },

4
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgf119.c
View File

@ -31,10 +31,8 @@ gf119_disp_root = {
.dmac = {
&gf119_disp_core_oclass,
},
.pioc = {
&gf119_disp_curs_oclass,
},
.user = {
{{0,0,GF110_DISP_CURSOR }, gf119_disp_curs_new },
{{0,0,GF110_DISP_OVERLAY }, gf119_disp_oimm_new },
{{0,0,GF110_DISP_BASE_CHANNEL_DMA }, gf119_disp_base_new },
{{0,0,GF110_DISP_OVERLAY_CONTROL_DMA}, gf119_disp_ovly_new },

4
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgk104.c
View File

@ -31,10 +31,8 @@ gk104_disp_root = {
.dmac = {
&gk104_disp_core_oclass,
},
.pioc = {
&gk104_disp_curs_oclass,
},
.user = {
{{0,0,GK104_DISP_CURSOR }, gf119_disp_curs_new },
{{0,0,GK104_DISP_OVERLAY }, gf119_disp_oimm_new },
{{0,0,GK104_DISP_BASE_CHANNEL_DMA }, gf119_disp_base_new },
{{0,0,GK104_DISP_OVERLAY_CONTROL_DMA}, gk104_disp_ovly_new },

4
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgk110.c
View File

@ -31,10 +31,8 @@ gk110_disp_root = {
.dmac = {
&gk110_disp_core_oclass,
},
.pioc = {
&gk104_disp_curs_oclass,
},
.user = {
{{0,0,GK104_DISP_CURSOR }, gf119_disp_curs_new },
{{0,0,GK104_DISP_OVERLAY }, gf119_disp_oimm_new },
{{0,0,GK110_DISP_BASE_CHANNEL_DMA }, gf119_disp_base_new },
{{0,0,GK104_DISP_OVERLAY_CONTROL_DMA}, gk104_disp_ovly_new },

4
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgm107.c
View File

@ -31,10 +31,8 @@ gm107_disp_root = {
.dmac = {
&gm107_disp_core_oclass,
},
.pioc = {
&gk104_disp_curs_oclass,
},
.user = {
{{0,0,GK104_DISP_CURSOR }, gf119_disp_curs_new },
{{0,0,GK104_DISP_OVERLAY }, gf119_disp_oimm_new },
{{0,0,GK110_DISP_BASE_CHANNEL_DMA }, gf119_disp_base_new },
{{0,0,GK104_DISP_OVERLAY_CONTROL_DMA}, gk104_disp_ovly_new },

4
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgm200.c
View File

@ -31,10 +31,8 @@ gm200_disp_root = {
.dmac = {
&gm200_disp_core_oclass,
},
.pioc = {
&gk104_disp_curs_oclass,
},
.user = {
{{0,0,GK104_DISP_CURSOR }, gf119_disp_curs_new },
{{0,0,GK104_DISP_OVERLAY }, gf119_disp_oimm_new },
{{0,0,GK110_DISP_BASE_CHANNEL_DMA }, gf119_disp_base_new },
{{0,0,GK104_DISP_OVERLAY_CONTROL_DMA}, gk104_disp_ovly_new },

4
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgp100.c
View File

@ -31,10 +31,8 @@ gp100_disp_root = {
.dmac = {
&gp100_disp_core_oclass,
},
.pioc = {
&gk104_disp_curs_oclass,
},
.user = {
{{0,0,GK104_DISP_CURSOR }, gf119_disp_curs_new },
{{0,0,GK104_DISP_OVERLAY }, gf119_disp_oimm_new },
{{0,0,GK110_DISP_BASE_CHANNEL_DMA }, gf119_disp_base_new },
{{0,0,GK104_DISP_OVERLAY_CONTROL_DMA}, gk104_disp_ovly_new },

4
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgp102.c
View File

@ -31,10 +31,8 @@ gp102_disp_root = {
.dmac = {
&gp102_disp_core_oclass,
},
.pioc = {
&gp102_disp_curs_oclass,
},
.user = {
{{0,0,GK104_DISP_CURSOR }, gp102_disp_curs_new },
{{0,0,GK104_DISP_OVERLAY }, gp102_disp_oimm_new },
{{0,0,GK110_DISP_BASE_CHANNEL_DMA }, gp102_disp_base_new },
{{0,0,GK104_DISP_OVERLAY_CONTROL_DMA}, gp102_disp_ovly_new },

4
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgt200.c
View File

@ -31,10 +31,8 @@ gt200_disp_root = {
.dmac = {
&gt200_disp_core_oclass,
},
.pioc = {
&g84_disp_curs_oclass,
},
.user = {
{{0,0, G82_DISP_CURSOR }, nv50_disp_curs_new },
{{0,0, G82_DISP_OVERLAY }, nv50_disp_oimm_new },
{{0,0,GT200_DISP_BASE_CHANNEL_DMA }, g84_disp_base_new },
{{0,0,GT200_DISP_OVERLAY_CHANNEL_DMA}, gt200_disp_ovly_new },

4
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootgt215.c
View File

@ -31,10 +31,8 @@ gt215_disp_root = {
.dmac = {
&gt215_disp_core_oclass,
},
.pioc = {
&gt215_disp_curs_oclass,
},
.user = {
{{0,0,GT214_DISP_CURSOR }, nv50_disp_curs_new },
{{0,0,GT214_DISP_OVERLAY }, nv50_disp_oimm_new },
{{0,0,GT214_DISP_BASE_CHANNEL_DMA }, g84_disp_base_new },
{{0,0,GT214_DISP_OVERLAY_CHANNEL_DMA}, g84_disp_ovly_new },

23
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c
View File

@ -278,16 +278,6 @@ nv50_disp_root_dmac_new_(const struct nvkm_oclass *oclass,
oclass, data, size, pobject);
}
static int
nv50_disp_root_pioc_new_(const struct nvkm_oclass *oclass,
void *data, u32 size, struct nvkm_object **pobject)
{
const struct nv50_disp_pioc_oclass *sclass = oclass->priv;
struct nv50_disp_root *root = nv50_disp_root(oclass->parent);
return sclass->ctor(sclass->func, sclass->mthd, root, sclass->chid.ctrl,
sclass->chid.user, oclass, data, size, pobject);
}
static int
nv50_disp_root_child_new_(const struct nvkm_oclass *oclass,
void *argv, u32 argc, struct nvkm_object **pobject)
@ -312,15 +302,6 @@ nv50_disp_root_child_get_(struct nvkm_object *object, int index,
index -= ARRAY_SIZE(root->func->dmac);
if (index < ARRAY_SIZE(root->func->pioc)) {
sclass->base = root->func->pioc[index]->base;
sclass->priv = root->func->pioc[index];
sclass->ctor = nv50_disp_root_pioc_new_;
return 0;
}
index -= ARRAY_SIZE(root->func->pioc);
if (root->func->user[index].ctor) {
sclass->base = root->func->user[index].base;
sclass->priv = root->func->user + index;
@ -369,10 +350,8 @@ nv50_disp_root = {
.dmac = {
&nv50_disp_core_oclass,
},
.pioc = {
&nv50_disp_curs_oclass,
},
.user = {
{{0,0,NV50_DISP_CURSOR }, nv50_disp_curs_new },
{{0,0,NV50_DISP_OVERLAY }, nv50_disp_oimm_new },
{{0,0,NV50_DISP_BASE_CHANNEL_DMA }, nv50_disp_base_new },
{{0,0,NV50_DISP_OVERLAY_CHANNEL_DMA}, nv50_disp_ovly_new },

2
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.h
View File

@ -3,7 +3,6 @@
#define __NV50_DISP_ROOT_H__
#define nv50_disp_root(p) container_of((p), struct nv50_disp_root, object)
#include "nv50.h"
#include "channv50.h"
#include "dmacnv50.h"
struct nv50_disp_root {
@ -14,7 +13,6 @@ struct nv50_disp_root {
struct nv50_disp_root_func {
const struct nv50_disp_dmac_oclass *dmac[1];
const struct nv50_disp_pioc_oclass *pioc[1];
struct nv50_disp_user {
struct nvkm_sclass base;
int (*ctor)(const struct nvkm_oclass *, void *argv, u32 argc,