sh: Add SH7203 CPU support.
This adds support for the SH7203 (SH-2A) CPU. Signed-off-by: Kieran Bingham <kbingham@mpc-data.co.uk> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Paul Mundt
parent
ff1b750605
commit
6d01f51086
@ -158,6 +158,10 @@ config CPU_SUBTYPE_SH7619
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# SH-2A Processor Support
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config CPU_SUBTYPE_SH7203
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bool "Support SH7203 processor"
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select CPU_SH2A
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config CPU_SUBTYPE_SH7206
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bool "Support SH7206 processor"
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select CPU_SH2A
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@ -556,7 +560,7 @@ config SH_PCLK_FREQ
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default "32000000" if CPU_SUBTYPE_SH7722
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default "33333333" if CPU_SUBTYPE_SH7770 || \
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CPU_SUBTYPE_SH7760 || CPU_SUBTYPE_SH7705 || \
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CPU_SUBTYPE_SH7206
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CPU_SUBTYPE_SH7203 || CPU_SUBTYPE_SH7206
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default "60000000" if CPU_SUBTYPE_SH7751 || CPU_SUBTYPE_SH7751R
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default "66000000" if CPU_SUBTYPE_SH4_202
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default "50000000"
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@ -567,7 +571,7 @@ config SH_PCLK_FREQ
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config SH_CLK_MD
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int "CPU Mode Pin Setting"
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depends on CPU_SUBTYPE_SH7619 || CPU_SUBTYPE_SH7206
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depends on CPU_SH2
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default 6 if CPU_SUBTYPE_SH7206
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default 5 if CPU_SUBTYPE_SH7619
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default 0
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@ -32,6 +32,7 @@ config EARLY_SCIF_CONSOLE_PORT
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depends on EARLY_SCIF_CONSOLE
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default "0xffe00000" if CPU_SUBTYPE_SH7780
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default "0xffea0000" if CPU_SUBTYPE_SH7785
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default "0xfffe8000" if CPU_SUBTYPE_SH7203
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default "0xfffe9800" if CPU_SUBTYPE_SH7206
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default "0xf8420000" if CPU_SUBTYPE_SH7619
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default "0xa4400000" if CPU_SUBTYPE_SH7712 || CPU_SUBTYPE_SH7705
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@ -7,3 +7,4 @@ obj-y := common.o probe.o opcode_helper.o
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common-y += $(addprefix ../sh2/, ex.o entry.o)
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obj-$(CONFIG_CPU_SUBTYPE_SH7206) += setup-sh7206.o clock-sh7206.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7203) += setup-sh7203.o clock-sh7203.o
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89
arch/sh/kernel/cpu/sh2a/clock-sh7203.c
Normal file
89
arch/sh/kernel/cpu/sh2a/clock-sh7203.c
Normal file
@ -0,0 +1,89 @@
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/*
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* arch/sh/kernel/cpu/sh2a/clock-sh7203.c
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*
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* SH7203 support for the clock framework
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*
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* Copyright (C) 2007 Kieran Bingham (MPC-Data Ltd)
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*
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* Based on clock-sh7263.c
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* Copyright (C) 2006 Yoshinori Sato
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*
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* Based on clock-sh4.c
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* Copyright (C) 2005 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <asm/clock.h>
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#include <asm/freq.h>
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#include <asm/io.h>
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const static int pll1rate[]={8,12,16,0};
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const static int pfc_divisors[]={1,2,3,4,6,8,12};
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#define ifc_divisors pfc_divisors
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#if (CONFIG_SH_CLK_MD == 0)
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#define PLL2 (1)
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#elif (CONFIG_SH_CLK_MD == 1)
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#define PLL2 (2)
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#elif (CONFIG_SH_CLK_MD == 2)
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#define PLL2 (4)
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#elif (CONFIG_SH_CLK_MD == 3)
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#define PLL2 (4)
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#else
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#error "Illegal Clock Mode!"
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#endif
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static void master_clk_init(struct clk *clk)
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{
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clk->rate *= pll1rate[(ctrl_inw(FREQCR) >> 8) & 0x0003] * PLL2 ;
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}
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static struct clk_ops sh7203_master_clk_ops = {
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.init = master_clk_init,
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};
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static void module_clk_recalc(struct clk *clk)
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{
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int idx = (ctrl_inw(FREQCR) & 0x0007);
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clk->rate = clk->parent->rate / pfc_divisors[idx];
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}
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static struct clk_ops sh7203_module_clk_ops = {
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.recalc = module_clk_recalc,
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};
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static void bus_clk_recalc(struct clk *clk)
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{
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int idx = (ctrl_inw(FREQCR) & 0x0007);
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clk->rate = clk->parent->rate / pfc_divisors[idx-2];
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}
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static struct clk_ops sh7203_bus_clk_ops = {
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.recalc = bus_clk_recalc,
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};
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static void cpu_clk_recalc(struct clk *clk)
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{
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clk->rate = clk->parent->rate;
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}
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static struct clk_ops sh7203_cpu_clk_ops = {
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.recalc = cpu_clk_recalc,
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};
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static struct clk_ops *sh7203_clk_ops[] = {
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&sh7203_master_clk_ops,
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&sh7203_module_clk_ops,
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&sh7203_bus_clk_ops,
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&sh7203_cpu_clk_ops,
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};
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void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
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{
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if (idx < ARRAY_SIZE(sh7203_clk_ops))
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*ops = sh7203_clk_ops[idx];
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}
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@ -3,25 +3,33 @@
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*
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* CPU Subtype Probing for SH-2A.
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*
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* Copyright (C) 2004, 2005 Paul Mundt
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* Copyright (C) 2004 - 2007 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <asm/processor.h>
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#include <asm/cache.h>
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int __init detect_cpu_and_cache_system(void)
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{
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/* Just SH7206 for now .. */
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boot_cpu_data.type = CPU_SH7206;
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/* All SH-2A CPUs have support for 16 and 32-bit opcodes.. */
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boot_cpu_data.flags |= CPU_HAS_OP32;
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#if defined(CONFIG_CPU_SUBTYPE_SH7203)
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boot_cpu_data.type = CPU_SH7203;
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/* SH7203 has an FPU.. */
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boot_cpu_data.flags |= CPU_HAS_FPU;
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#elif defined(CONFIG_CPU_SUBTYPE_SH7206)
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boot_cpu_data.type = CPU_SH7206;
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/* While SH7206 has a DSP.. */
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boot_cpu_data.flags |= CPU_HAS_DSP;
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#endif
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boot_cpu_data.dcache.ways = 4;
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boot_cpu_data.dcache.way_incr = (1 << 11);
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boot_cpu_data.dcache.way_incr = (1 << 11);
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boot_cpu_data.dcache.sets = 128;
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boot_cpu_data.dcache.entry_shift = 4;
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boot_cpu_data.dcache.linesz = L1_CACHE_BYTES;
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@ -37,4 +45,3 @@ int __init detect_cpu_and_cache_system(void)
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return 0;
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}
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281
arch/sh/kernel/cpu/sh2a/setup-sh7203.c
Normal file
281
arch/sh/kernel/cpu/sh2a/setup-sh7203.c
Normal file
@ -0,0 +1,281 @@
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/*
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* SH7203 Setup
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*
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* Copyright (C) 2007 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/platform_device.h>
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#include <linux/init.h>
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#include <linux/serial.h>
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#include <asm/sci.h>
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enum {
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UNUSED = 0,
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/* interrupt sources */
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IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
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PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
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DMAC0_DEI, DMAC0_HEI, DMAC1_DEI, DMAC1_HEI,
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DMAC2_DEI, DMAC2_HEI, DMAC3_DEI, DMAC3_HEI,
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DMAC4_DEI, DMAC4_HEI, DMAC5_DEI, DMAC5_HEI,
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DMAC6_DEI, DMAC6_HEI, DMAC7_DEI, DMAC7_HEI,
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USB, LCDC, CMT0, CMT1, BSC, WDT,
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MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D,
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MTU2_TCI0V, MTU2_TGI0E, MTU2_TGI0F,
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MTU2_TGI1A, MTU2_TGI1B, MTU2_TCI1V, MTU2_TCI1U,
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MTU2_TGI2A, MTU2_TGI2B, MTU2_TCI2V, MTU2_TCI2U,
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MTU2_TGI3A, MTU2_TGI3B, MTU2_TGI3C, MTU2_TGI3D, MTU2_TCI3V,
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MTU2_TGI4A, MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D, MTU2_TCI4V,
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ADC_ADI,
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IIC30_STPI, IIC30_NAKI, IIC30_RXI, IIC30_TXI, IIC30_TEI,
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IIC31_STPI, IIC31_NAKI, IIC31_RXI, IIC31_TXI, IIC31_TEI,
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IIC32_STPI, IIC32_NAKI, IIC32_RXI, IIC32_TXI, IIC32_TEI,
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IIC33_STPI, IIC33_NAKI, IIC33_RXI, IIC33_TXI, IIC33_TEI,
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SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI,
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SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI,
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SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI,
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SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI,
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SSU0_SSERI, SSU0_SSRXI, SSU0_SSTXI,
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SSU1_SSERI, SSU1_SSRXI, SSU1_SSTXI,
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SSI0_SSII, SSI1_SSII, SSI2_SSII, SSI3_SSII,
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FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
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RTC_ARM, RTC_PRD, RTC_CUP,
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RCAN0_ERS, RCAN0_OVR, RCAN0_RM0, RCAN0_RM1, RCAN0_SLE,
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RCAN1_ERS, RCAN1_OVR, RCAN1_RM0, RCAN1_RM1, RCAN1_SLE,
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/* interrupt groups */
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PINT, DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7,
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MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU,
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MTU3_ABCD, MTU4_ABCD,
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IIC30, IIC31, IIC32, IIC33, SCIF0, SCIF1, SCIF2, SCIF3,
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SSU0, SSU1, FLCTL, RTC, RCAN0, RCAN1
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};
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static struct intc_vect vectors[] __initdata = {
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INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
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INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
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INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
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INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
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INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
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INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
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INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
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INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
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INTC_IRQ(DMAC0_DEI, 108), INTC_IRQ(DMAC0_HEI, 109),
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INTC_IRQ(DMAC1_DEI, 112), INTC_IRQ(DMAC1_HEI, 113),
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INTC_IRQ(DMAC2_DEI, 116), INTC_IRQ(DMAC2_HEI, 117),
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INTC_IRQ(DMAC3_DEI, 120), INTC_IRQ(DMAC3_HEI, 121),
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INTC_IRQ(DMAC4_DEI, 124), INTC_IRQ(DMAC4_HEI, 125),
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INTC_IRQ(DMAC5_DEI, 128), INTC_IRQ(DMAC5_HEI, 129),
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INTC_IRQ(DMAC6_DEI, 132), INTC_IRQ(DMAC6_HEI, 133),
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INTC_IRQ(DMAC7_DEI, 136), INTC_IRQ(DMAC7_HEI, 137),
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INTC_IRQ(USB, 140), INTC_IRQ(LCDC, 141),
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INTC_IRQ(CMT0, 142), INTC_IRQ(CMT1, 143),
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INTC_IRQ(BSC, 144), INTC_IRQ(WDT, 145),
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INTC_IRQ(MTU2_TGI0A, 146), INTC_IRQ(MTU2_TGI0B, 147),
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INTC_IRQ(MTU2_TGI0C, 148), INTC_IRQ(MTU2_TGI0D, 149),
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INTC_IRQ(MTU2_TCI0V, 150),
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INTC_IRQ(MTU2_TGI0E, 151), INTC_IRQ(MTU2_TGI0F, 152),
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INTC_IRQ(MTU2_TGI1A, 153), INTC_IRQ(MTU2_TGI1B, 154),
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INTC_IRQ(MTU2_TCI1V, 155), INTC_IRQ(MTU2_TCI1U, 156),
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INTC_IRQ(MTU2_TGI2A, 157), INTC_IRQ(MTU2_TGI2B, 158),
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INTC_IRQ(MTU2_TCI2V, 159), INTC_IRQ(MTU2_TCI2U, 160),
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INTC_IRQ(MTU2_TGI3A, 161), INTC_IRQ(MTU2_TGI3B, 162),
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INTC_IRQ(MTU2_TGI3C, 163), INTC_IRQ(MTU2_TGI3D, 164),
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INTC_IRQ(MTU2_TCI3V, 165),
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INTC_IRQ(MTU2_TGI4A, 166), INTC_IRQ(MTU2_TGI4B, 167),
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INTC_IRQ(MTU2_TGI4C, 168), INTC_IRQ(MTU2_TGI4D, 169),
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INTC_IRQ(MTU2_TCI4V, 170),
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INTC_IRQ(ADC_ADI, 171),
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INTC_IRQ(IIC30_STPI, 172), INTC_IRQ(IIC30_NAKI, 173),
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INTC_IRQ(IIC30_RXI, 174), INTC_IRQ(IIC30_TXI, 175),
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INTC_IRQ(IIC30_TEI, 176),
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INTC_IRQ(IIC31_STPI, 177), INTC_IRQ(IIC31_NAKI, 178),
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INTC_IRQ(IIC31_RXI, 179), INTC_IRQ(IIC31_TXI, 180),
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INTC_IRQ(IIC31_TEI, 181),
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INTC_IRQ(IIC32_STPI, 182), INTC_IRQ(IIC32_NAKI, 183),
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INTC_IRQ(IIC32_RXI, 184), INTC_IRQ(IIC32_TXI, 185),
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INTC_IRQ(IIC32_TEI, 186),
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INTC_IRQ(IIC33_STPI, 187), INTC_IRQ(IIC33_NAKI, 188),
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INTC_IRQ(IIC33_RXI, 189), INTC_IRQ(IIC33_TXI, 190),
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INTC_IRQ(IIC33_TEI, 191),
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INTC_IRQ(SCIF0_BRI, 192), INTC_IRQ(SCIF0_ERI, 193),
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INTC_IRQ(SCIF0_RXI, 194), INTC_IRQ(SCIF0_TXI, 195),
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INTC_IRQ(SCIF1_BRI, 196), INTC_IRQ(SCIF1_ERI, 197),
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INTC_IRQ(SCIF1_RXI, 198), INTC_IRQ(SCIF1_TXI, 199),
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INTC_IRQ(SCIF2_BRI, 200), INTC_IRQ(SCIF2_ERI, 201),
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INTC_IRQ(SCIF2_RXI, 202), INTC_IRQ(SCIF2_TXI, 203),
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INTC_IRQ(SCIF3_BRI, 204), INTC_IRQ(SCIF3_ERI, 205),
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INTC_IRQ(SCIF3_RXI, 206), INTC_IRQ(SCIF3_TXI, 207),
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INTC_IRQ(SSU0_SSERI, 208), INTC_IRQ(SSU0_SSRXI, 209),
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INTC_IRQ(SSU0_SSTXI, 210),
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INTC_IRQ(SSU1_SSERI, 211), INTC_IRQ(SSU1_SSRXI, 212),
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INTC_IRQ(SSU1_SSTXI, 213),
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INTC_IRQ(SSI0_SSII, 214), INTC_IRQ(SSI1_SSII, 215),
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INTC_IRQ(SSI2_SSII, 216), INTC_IRQ(SSI3_SSII, 217),
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INTC_IRQ(FLCTL_FLSTEI, 224), INTC_IRQ(FLCTL_FLTENDI, 225),
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INTC_IRQ(FLCTL_FLTREQ0I, 226), INTC_IRQ(FLCTL_FLTREQ1I, 227),
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INTC_IRQ(RTC_ARM, 231), INTC_IRQ(RTC_PRD, 232),
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INTC_IRQ(RTC_CUP, 233),
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INTC_IRQ(RCAN0_ERS, 234), INTC_IRQ(RCAN0_OVR, 235),
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INTC_IRQ(RCAN0_RM0, 236), INTC_IRQ(RCAN0_RM1, 237),
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INTC_IRQ(RCAN0_SLE, 238),
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INTC_IRQ(RCAN1_ERS, 239), INTC_IRQ(RCAN1_OVR, 240),
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INTC_IRQ(RCAN1_RM0, 241), INTC_IRQ(RCAN1_RM1, 242),
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INTC_IRQ(RCAN1_SLE, 243),
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};
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static struct intc_group groups[] __initdata = {
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INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
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PINT4, PINT5, PINT6, PINT7),
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INTC_GROUP(DMAC0, DMAC0_DEI, DMAC0_HEI),
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INTC_GROUP(DMAC1, DMAC1_DEI, DMAC1_HEI),
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INTC_GROUP(DMAC2, DMAC2_DEI, DMAC2_HEI),
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INTC_GROUP(DMAC3, DMAC3_DEI, DMAC3_HEI),
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INTC_GROUP(DMAC4, DMAC4_DEI, DMAC4_HEI),
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INTC_GROUP(DMAC5, DMAC5_DEI, DMAC5_HEI),
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INTC_GROUP(DMAC6, DMAC6_DEI, DMAC6_HEI),
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INTC_GROUP(DMAC7, DMAC7_DEI, DMAC7_HEI),
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INTC_GROUP(MTU0_ABCD, MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D),
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INTC_GROUP(MTU0_VEF, MTU2_TCI0V, MTU2_TGI0E, MTU2_TGI0F),
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INTC_GROUP(MTU1_AB, MTU2_TGI1A, MTU2_TGI1B),
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INTC_GROUP(MTU1_VU, MTU2_TCI1V, MTU2_TCI1U),
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INTC_GROUP(MTU2_AB, MTU2_TGI2A, MTU2_TGI2B),
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INTC_GROUP(MTU2_VU, MTU2_TCI2V, MTU2_TCI2U),
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INTC_GROUP(MTU3_ABCD, MTU2_TGI3A, MTU2_TGI3B, MTU2_TGI3C, MTU2_TGI3D),
|
||||
INTC_GROUP(MTU4_ABCD, MTU2_TGI4A, MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D),
|
||||
INTC_GROUP(IIC30, IIC30_STPI, IIC30_NAKI, IIC30_RXI, IIC30_TXI,
|
||||
IIC30_TEI),
|
||||
INTC_GROUP(IIC31, IIC31_STPI, IIC31_NAKI, IIC31_RXI, IIC31_TXI,
|
||||
IIC31_TEI),
|
||||
INTC_GROUP(IIC32, IIC32_STPI, IIC32_NAKI, IIC32_RXI, IIC32_TXI,
|
||||
IIC32_TEI),
|
||||
INTC_GROUP(IIC33, IIC33_STPI, IIC33_NAKI, IIC33_RXI, IIC33_TXI,
|
||||
IIC33_TEI),
|
||||
INTC_GROUP(SCIF0, SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI),
|
||||
INTC_GROUP(SCIF1, SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI),
|
||||
INTC_GROUP(SCIF2, SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI),
|
||||
INTC_GROUP(SCIF3, SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI),
|
||||
INTC_GROUP(SSU0, SSU0_SSERI, SSU0_SSRXI, SSU0_SSTXI),
|
||||
INTC_GROUP(SSU1, SSU1_SSERI, SSU1_SSRXI, SSU1_SSTXI),
|
||||
INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I,
|
||||
FLCTL_FLTREQ1I),
|
||||
INTC_GROUP(RTC, RTC_ARM, RTC_PRD, RTC_CUP),
|
||||
INTC_GROUP(RCAN0, RCAN0_ERS, RCAN0_OVR, RCAN0_RM0, RCAN0_RM1,
|
||||
RCAN0_SLE),
|
||||
INTC_GROUP(RCAN1, RCAN1_ERS, RCAN1_OVR, RCAN1_RM0, RCAN1_RM1,
|
||||
RCAN1_SLE),
|
||||
};
|
||||
|
||||
static struct intc_prio_reg prio_registers[] __initdata = {
|
||||
{ 0xfffe0818, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
|
||||
{ 0xfffe081a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
|
||||
{ 0xfffe0820, 0, 16, 4, /* IPR05 */ { PINT, 0, 0, 0 } },
|
||||
{ 0xfffe0c00, 0, 16, 4, /* IPR06 */ { DMAC0, DMAC1, DMAC2, DMAC3 } },
|
||||
{ 0xfffe0c02, 0, 16, 4, /* IPR07 */ { DMAC4, DMAC5, DMAC6, DMAC7 } },
|
||||
{ 0xfffe0c04, 0, 16, 4, /* IPR08 */ { USB, LCDC, CMT0, CMT1 } },
|
||||
{ 0xfffe0c06, 0, 16, 4, /* IPR09 */ { BSC, WDT, MTU0_ABCD, MTU0_VEF } },
|
||||
{ 0xfffe0c08, 0, 16, 4, /* IPR10 */ { MTU1_AB, MTU1_VU, MTU2_AB,
|
||||
MTU2_VU } },
|
||||
{ 0xfffe0c0a, 0, 16, 4, /* IPR11 */ { MTU3_ABCD, MTU2_TCI3V, MTU4_ABCD,
|
||||
MTU2_TCI4V } },
|
||||
{ 0xfffe0c0c, 0, 16, 4, /* IPR12 */ { ADC_ADI, IIC30, IIC31, IIC32 } },
|
||||
{ 0xfffe0c0e, 0, 16, 4, /* IPR13 */ { IIC33, SCIF0, SCIF1, SCIF2 } },
|
||||
{ 0xfffe0c10, 0, 16, 4, /* IPR14 */ { SCIF3, SSU0, SSU1, SSI0_SSII } },
|
||||
{ 0xfffe0c12, 0, 16, 4, /* IPR15 */ { SSI1_SSII, SSI2_SSII,
|
||||
SSI3_SSII, 0 } },
|
||||
{ 0xfffe0c14, 0, 16, 4, /* IPR16 */ { FLCTL, 0, RTC, RCAN0 } },
|
||||
{ 0xfffe0c16, 0, 16, 4, /* IPR17 */ { RCAN1, 0, 0, 0 } },
|
||||
};
|
||||
|
||||
static struct intc_mask_reg mask_registers[] __initdata = {
|
||||
{ 0xfffe0808, 0, 16, /* PINTER */
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
|
||||
};
|
||||
|
||||
static DECLARE_INTC_DESC(intc_desc, "sh7203", vectors, groups,
|
||||
NULL, mask_registers, prio_registers, NULL);
|
||||
|
||||
static struct plat_sci_port sci_platform_data[] = {
|
||||
{
|
||||
.mapbase = 0xfffe8000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 193, 194, 195, 192 },
|
||||
}, {
|
||||
.mapbase = 0xfffe8800,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 197, 198, 199, 196 },
|
||||
}, {
|
||||
.mapbase = 0xfffe9000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 201, 202, 203, 200 },
|
||||
}, {
|
||||
.mapbase = 0xfffe9800,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 205, 206, 207, 204 },
|
||||
}, {
|
||||
.flags = 0,
|
||||
}
|
||||
};
|
||||
|
||||
static struct platform_device sci_device = {
|
||||
.name = "sh-sci",
|
||||
.id = -1,
|
||||
.dev = {
|
||||
.platform_data = sci_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct resource rtc_resources[] = {
|
||||
[0] = {
|
||||
.start = 0xffff2000,
|
||||
.end = 0xffff2000 + 0x58 - 1,
|
||||
.flags = IORESOURCE_IO,
|
||||
},
|
||||
[1] = {
|
||||
/* Period IRQ */
|
||||
.start = 232,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
[2] = {
|
||||
/* Carry IRQ */
|
||||
.start = 233,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
[3] = {
|
||||
/* Alarm IRQ */
|
||||
.start = 231,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device rtc_device = {
|
||||
.name = "sh-rtc",
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(rtc_resources),
|
||||
.resource = rtc_resources,
|
||||
};
|
||||
|
||||
static struct platform_device *sh7203_devices[] __initdata = {
|
||||
&sci_device,
|
||||
&rtc_device,
|
||||
};
|
||||
|
||||
static int __init sh7203_devices_setup(void)
|
||||
{
|
||||
return platform_add_devices(sh7203_devices,
|
||||
ARRAY_SIZE(sh7203_devices));
|
||||
}
|
||||
__initcall(sh7203_devices_setup);
|
||||
|
||||
void __init plat_irq_setup(void)
|
||||
{
|
||||
register_intc_controller(&intc_desc);
|
||||
}
|
||||
@ -294,6 +294,7 @@ void __init setup_arch(char **cmdline_p)
|
||||
}
|
||||
|
||||
static const char *cpu_name[] = {
|
||||
[CPU_SH7203] = "SH7203",
|
||||
[CPU_SH7206] = "SH7206", [CPU_SH7619] = "SH7619",
|
||||
[CPU_SH7705] = "SH7705", [CPU_SH7706] = "SH7706",
|
||||
[CPU_SH7707] = "SH7707", [CPU_SH7708] = "SH7708",
|
||||
|
||||
@ -31,7 +31,7 @@
|
||||
#define cmt_clock_enable() do { ctrl_outb(ctrl_inb(STBCR3) & ~0x10, STBCR3); } while(0)
|
||||
#define CMT_CMCSR_INIT 0x0040
|
||||
#define CMT_CMCSR_CALIB 0x0000
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7206)
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7203) || defined(CONFIG_CPU_SUBTYPE_SH7206)
|
||||
#define CMT_CMSTR 0xfffec000
|
||||
#define CMT_CMCSR_0 0xfffec002
|
||||
#define CMT_CMCNT_0 0xfffec004
|
||||
|
||||
@ -142,7 +142,8 @@
|
||||
# define SCIF_OPER 0x0001 /* Overrun error bit */
|
||||
# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
|
||||
# define SCIF_ONLY
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7206)
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7203) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7206)
|
||||
# define SCSPTR0 0xfffe8020 /* 16 bit SCIF */
|
||||
# define SCSPTR1 0xfffe8820 /* 16 bit SCIF */
|
||||
# define SCSPTR2 0xfffe9020 /* 16 bit SCIF */
|
||||
@ -617,7 +618,8 @@ static inline int sci_rxd_in(struct uart_port *port)
|
||||
return ctrl_inw(SCSPTR5) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
return 1;
|
||||
}
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7206)
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7203) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7206)
|
||||
static inline int sci_rxd_in(struct uart_port *port)
|
||||
{
|
||||
if (port->mapbase == 0xfffe8000)
|
||||
|
||||
@ -25,7 +25,7 @@ static void __init check_bugs(void)
|
||||
case CPU_SH7619:
|
||||
*p++ = '2';
|
||||
break;
|
||||
case CPU_SH7206:
|
||||
case CPU_SH7203 ... CPU_SH7206:
|
||||
*p++ = '2';
|
||||
*p++ = 'a';
|
||||
break;
|
||||
|
||||
@ -10,9 +10,7 @@
|
||||
#ifndef __ASM_CPU_SH2A_FREQ_H
|
||||
#define __ASM_CPU_SH2A_FREQ_H
|
||||
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7206)
|
||||
#define FREQCR 0xfffe0010
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_CPU_SH2A_FREQ_H */
|
||||
|
||||
|
||||
@ -17,7 +17,7 @@ enum cpu_type {
|
||||
CPU_SH7619,
|
||||
|
||||
/* SH-2A types */
|
||||
CPU_SH7206,
|
||||
CPU_SH7203, CPU_SH7206,
|
||||
|
||||
/* SH-3 types */
|
||||
CPU_SH7705, CPU_SH7706, CPU_SH7707,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user