forked from Minki/linux
ata: pata_hpt3x2n: pass base DPLL frequency to hpt3x2n_pci_clock()
Currently, the base DPLL frequency is hardcoded in hpt3x2n_pci_clock(). Align with the updated 'pata_hpt37x' driver, where this frequency is a parameter to hpt37x_pci_clock(). While at it, also do the following to align with the 'pata_hpt37x' driver: - fix the 'freq' local variable's type; - remove the 'iobase' local variable; - extend the comment to the inl() call; - move the 'total' local variable's declaration. Signed-off-by: Sergey Shtylyov <s.shtylyov@omp.ru> Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
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@ -24,7 +24,7 @@
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#include <linux/libata.h>
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#define DRV_NAME "pata_hpt3x2n"
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#define DRV_VERSION "0.3.18"
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#define DRV_VERSION "0.3.19"
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enum {
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PCI66 = (1 << 1),
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@ -403,17 +403,20 @@ static int hpt3xn_calibrate_dpll(struct pci_dev *dev)
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return 0;
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}
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static int hpt3x2n_pci_clock(struct pci_dev *pdev)
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static int hpt3x2n_pci_clock(struct pci_dev *pdev, unsigned int base)
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{
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unsigned long freq;
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unsigned int freq;
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u32 fcnt;
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unsigned long iobase = pci_resource_start(pdev, 4);
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fcnt = inl(iobase + 0x90); /* Not PCI readable for some chips */
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/*
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* Some devices do not let this value be accessed via PCI space
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* according to the old driver.
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*/
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fcnt = inl(pci_resource_start(pdev, 4) + 0x90);
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if ((fcnt >> 12) != 0xABCDE) {
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u32 total = 0;
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int i;
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u16 sr;
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u32 total = 0;
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dev_warn(&pdev->dev, "BIOS clock data not set\n");
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@ -427,7 +430,7 @@ static int hpt3x2n_pci_clock(struct pci_dev *pdev)
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}
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fcnt &= 0x1FF;
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freq = (fcnt * 77) / 192;
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freq = (fcnt * base) / 192; /* in MHz */
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/* Clamp to bands */
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if (freq < 40)
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@ -559,7 +562,7 @@ hpt372n:
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* 50 for UDMA100. Right now we always use 66
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*/
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pci_mhz = hpt3x2n_pci_clock(dev);
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pci_mhz = hpt3x2n_pci_clock(dev, 77);
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f_low = (pci_mhz * 48) / 66; /* PCI Mhz for 66Mhz DPLL */
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f_high = f_low + 2; /* Tolerance */
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