ARM: proc-arm94*.S: fix setup function
Both ARM946 and ARM940 setup functions were corrupting r1 and r2, which is not permissible - these are used to carry the machine ID and boot data into the kernel, and must be preserved. The code responsible for this was the same in both files: they were using the registers to generate a protection region register value. Fix this by turning this process into a macro, and using that macro in both these files with an alternative register allocation. r0, r3 and r7 can be used for temporary values here. Reported-by: Alex Dumitrache <broscutamaker@gmail.com> Tested-by: Georg Hofstetter <g3gg0.de@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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				| @ -297,26 +297,16 @@ __arm940_setup: | ||||
| 	mcr	p15, 0, r0, c6,	c0, 1 | ||||
| 
 | ||||
| 	ldr	r0, =(CONFIG_DRAM_BASE & 0xFFFFF000) @ base[31:12] of RAM
 | ||||
| 	ldr	r1, =(CONFIG_DRAM_SIZE >> 12)	@ size of RAM (must be >= 4KB)
 | ||||
| 	mov	r2, #10				@ 11 is the minimum (4KB)
 | ||||
| 1:	add	r2, r2, #1			@ area size *= 2
 | ||||
| 	mov	r1, r1, lsr #1 | ||||
| 	bne	1b				@ count not zero r-shift
 | ||||
| 	orr	r0, r0, r2, lsl #1		@ the area register value
 | ||||
| 	orr	r0, r0, #1			@ set enable bit
 | ||||
| 	mcr	p15, 0, r0, c6,	c1, 0		@ set area 1, RAM
 | ||||
| 	mcr	p15, 0, r0, c6,	c1, 1 | ||||
| 	ldr	r7, =CONFIG_DRAM_SIZE >> 12	@ size of RAM (must be >= 4KB)
 | ||||
| 	pr_val	r3, r0, r7, #1 | ||||
| 	mcr	p15, 0, r3, c6,	c1, 0		@ set area 1, RAM
 | ||||
| 	mcr	p15, 0, r3, c6,	c1, 1 | ||||
| 
 | ||||
| 	ldr	r0, =(CONFIG_FLASH_MEM_BASE & 0xFFFFF000) @ base[31:12] of FLASH
 | ||||
| 	ldr	r1, =(CONFIG_FLASH_SIZE >> 12)	@ size of FLASH (must be >= 4KB)
 | ||||
| 	mov	r2, #10				@ 11 is the minimum (4KB)
 | ||||
| 1:	add	r2, r2, #1			@ area size *= 2
 | ||||
| 	mov	r1, r1, lsr #1 | ||||
| 	bne	1b				@ count not zero r-shift
 | ||||
| 	orr	r0, r0, r2, lsl #1		@ the area register value
 | ||||
| 	orr	r0, r0, #1			@ set enable bit
 | ||||
| 	mcr	p15, 0, r0, c6,	c2, 0		@ set area 2, ROM/FLASH
 | ||||
| 	mcr	p15, 0, r0, c6,	c2, 1 | ||||
| 	ldr	r7, =CONFIG_FLASH_SIZE		@ size of FLASH (must be >= 4KB)
 | ||||
| 	pr_val	r3, r0, r6, #1 | ||||
| 	mcr	p15, 0, r3, c6,	c2, 0		@ set area 2, ROM/FLASH
 | ||||
| 	mcr	p15, 0, r3, c6,	c2, 1 | ||||
| 
 | ||||
| 	mov	r0, #0x06 | ||||
| 	mcr	p15, 0, r0, c2, c0, 0		@ Region 1&2 cacheable
 | ||||
|  | ||||
| @ -343,24 +343,14 @@ __arm946_setup: | ||||
| 	mcr	p15, 0, r0, c6,	c0, 0		@ set region 0, default
 | ||||
| 
 | ||||
| 	ldr	r0, =(CONFIG_DRAM_BASE & 0xFFFFF000) @ base[31:12] of RAM
 | ||||
| 	ldr	r1, =(CONFIG_DRAM_SIZE >> 12)	@ size of RAM (must be >= 4KB)
 | ||||
| 	mov	r2, #10				@ 11 is the minimum (4KB)
 | ||||
| 1:	add	r2, r2, #1			@ area size *= 2
 | ||||
| 	mov	r1, r1, lsr #1 | ||||
| 	bne	1b				@ count not zero r-shift
 | ||||
| 	orr	r0, r0, r2, lsl #1		@ the region register value
 | ||||
| 	orr	r0, r0, #1			@ set enable bit
 | ||||
| 	mcr	p15, 0, r0, c6,	c1, 0		@ set region 1, RAM
 | ||||
| 	ldr	r7, =CONFIG_DRAM_SIZE		@ size of RAM (must be >= 4KB)
 | ||||
| 	pr_val	r3, r0, r7, #1 | ||||
| 	mcr	p15, 0, r3, c6, c1, 0 | ||||
| 
 | ||||
| 	ldr	r0, =(CONFIG_FLASH_MEM_BASE & 0xFFFFF000) @ base[31:12] of FLASH
 | ||||
| 	ldr	r1, =(CONFIG_FLASH_SIZE >> 12)	@ size of FLASH (must be >= 4KB)
 | ||||
| 	mov	r2, #10				@ 11 is the minimum (4KB)
 | ||||
| 1:	add	r2, r2, #1			@ area size *= 2
 | ||||
| 	mov	r1, r1, lsr #1 | ||||
| 	bne	1b				@ count not zero r-shift
 | ||||
| 	orr	r0, r0, r2, lsl #1		@ the region register value
 | ||||
| 	orr	r0, r0, #1			@ set enable bit
 | ||||
| 	mcr	p15, 0, r0, c6,	c2, 0		@ set region 2, ROM/FLASH
 | ||||
| 	ldr	r7, =CONFIG_FLASH_SIZE		@ size of FLASH (must be >= 4KB)
 | ||||
| 	pr_val	r3, r0, r7, #1 | ||||
| 	mcr	p15, 0, r3, c6, c2, 0 | ||||
| 
 | ||||
| 	mov	r0, #0x06 | ||||
| 	mcr	p15, 0, r0, c2, c0, 0		@ region 1,2 d-cacheable
 | ||||
|  | ||||
| @ -331,3 +331,27 @@ ENTRY(\name\()_tlb_fns) | ||||
| 	.globl	\x | ||||
| 	.equ	\x, \y | ||||
| .endm | ||||
| 
 | ||||
| 	/* | ||||
| 	 * Macro to calculate the log2 size for the protection region | ||||
| 	 * registers. This calculates rd = log2(size) - 1.  tmp must | ||||
| 	 * not be the same register as rd. | ||||
| 	 */ | ||||
| .macro	pr_sz, rd, size, tmp | ||||
| 	mov	\tmp, \size, lsr #12 | ||||
| 	mov	\rd, #11 | ||||
| 1:	movs	\tmp, \tmp, lsr #1 | ||||
| 	addne	\rd, \rd, #1 | ||||
| 	bne	1b | ||||
| .endm | ||||
| 
 | ||||
| 	/* | ||||
| 	 * Macro to generate a protection region register value | ||||
| 	 * given a pre-masked address, size, and enable bit. | ||||
| 	 * Corrupts size. | ||||
| 	 */ | ||||
| .macro	pr_val, dest, addr, size, enable | ||||
| 	pr_sz	\dest, \size, \size		@ calculate log2(size) - 1
 | ||||
| 	orr	\dest, \addr, \dest, lsl #1	@ mask in the region size
 | ||||
| 	orr	\dest, \dest, \enable | ||||
| .endm | ||||
|  | ||||
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