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drm/amdgpu: initialize vm_inv_eng0_sem for gfxhub and mmhub

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SW must acquire/release one of the vm_invalidate_eng*_sem around the
invalidation req/ack. Through this way,it can avoid losing invalidate
acknowledge state across power-gating off cycle.
To use vm_invalidate_eng*_sem, it needs to initialize
vm_invalidate_eng*_sem firstly.

Signed-off-by: changzhu <Changfeng.Zhu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
This commit is contained in:
changzhu
2019-11-19 10:18:39 +08:00
committed by Alex Deucher
parent 1b34de7c3f
commit 6c2c897237
6 changed files with 13 additions and 0 deletions
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1
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
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@@ -77,6 +77,7 @@ struct amdgpu_gmc_fault {
struct amdgpu_vmhub { struct amdgpu_vmhub {
uint32_t ctx0_ptb_addr_lo32; uint32_t ctx0_ptb_addr_lo32;
uint32_t ctx0_ptb_addr_hi32; uint32_t ctx0_ptb_addr_hi32;
uint32_t vm_inv_eng0_sem;
uint32_t vm_inv_eng0_req; uint32_t vm_inv_eng0_req;
uint32_t vm_inv_eng0_ack; uint32_t vm_inv_eng0_ack;
uint32_t vm_context0_cntl; uint32_t vm_context0_cntl;

2
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
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@@ -367,6 +367,8 @@ void gfxhub_v1_0_init(struct amdgpu_device *adev)
hub->ctx0_ptb_addr_hi32 = hub->ctx0_ptb_addr_hi32 =
SOC15_REG_OFFSET(GC, 0, SOC15_REG_OFFSET(GC, 0,
mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
hub->vm_inv_eng0_sem =
SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_SEM);
hub->vm_inv_eng0_req = hub->vm_inv_eng0_req =
SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_REQ); SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_REQ);
hub->vm_inv_eng0_ack = hub->vm_inv_eng0_ack =

2
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
View File

@@ -356,6 +356,8 @@ void gfxhub_v2_0_init(struct amdgpu_device *adev)
hub->ctx0_ptb_addr_hi32 = hub->ctx0_ptb_addr_hi32 =
SOC15_REG_OFFSET(GC, 0, SOC15_REG_OFFSET(GC, 0,
mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
hub->vm_inv_eng0_sem =
SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_SEM);
hub->vm_inv_eng0_req = hub->vm_inv_eng0_req =
SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_REQ); SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_REQ);
hub->vm_inv_eng0_ack = hub->vm_inv_eng0_ack =

2
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
View File

@@ -420,6 +420,8 @@ void mmhub_v1_0_init(struct amdgpu_device *adev)
hub->ctx0_ptb_addr_hi32 = hub->ctx0_ptb_addr_hi32 =
SOC15_REG_OFFSET(MMHUB, 0, SOC15_REG_OFFSET(MMHUB, 0,
mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
hub->vm_inv_eng0_sem =
SOC15_REG_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_SEM);
hub->vm_inv_eng0_req = hub->vm_inv_eng0_req =
SOC15_REG_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_REQ); SOC15_REG_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_REQ);
hub->vm_inv_eng0_ack = hub->vm_inv_eng0_ack =

2
drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
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@@ -348,6 +348,8 @@ void mmhub_v2_0_init(struct amdgpu_device *adev)
hub->ctx0_ptb_addr_hi32 = hub->ctx0_ptb_addr_hi32 =
SOC15_REG_OFFSET(MMHUB, 0, SOC15_REG_OFFSET(MMHUB, 0,
mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
hub->vm_inv_eng0_sem =
SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_SEM);
hub->vm_inv_eng0_req = hub->vm_inv_eng0_req =
SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_REQ); SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_REQ);
hub->vm_inv_eng0_ack = hub->vm_inv_eng0_ack =

4
drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
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@@ -504,6 +504,10 @@ void mmhub_v9_4_init(struct amdgpu_device *adev)
SOC15_REG_OFFSET(MMHUB, 0, SOC15_REG_OFFSET(MMHUB, 0,
mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32) + mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32) +
i * MMHUB_INSTANCE_REGISTER_OFFSET; i * MMHUB_INSTANCE_REGISTER_OFFSET;
hub[i]->vm_inv_eng0_sem =
SOC15_REG_OFFSET(MMHUB, 0,
mmVML2VC0_VM_INVALIDATE_ENG0_SEM) +
i * MMHUB_INSTANCE_REGISTER_OFFSET;
hub[i]->vm_inv_eng0_req = hub[i]->vm_inv_eng0_req =
SOC15_REG_OFFSET(MMHUB, 0, SOC15_REG_OFFSET(MMHUB, 0,
mmVML2VC0_VM_INVALIDATE_ENG0_REQ) + mmVML2VC0_VM_INVALIDATE_ENG0_REQ) +