ARM: OMAP4: Ctrl module register define diet
The mach-omap2 directory contains full register defines for OMAP4 control module but only around 27 of those are used. There are is a total of 1795 register defines in four files with only 27 in use. That is pretty low usefulness ratio... I guess alot more was used when we had omap4 board files and mach-omap2 contained more drivers but this has now changed. Signed-off-by: Joachim Eastwood <manabian@gmail.com> [tony@atomide.com: updated to apply] Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Joachim Eastwood
Tony Lindgren
parent
cd3de83f14
commit
6bf5885959
@ -16,11 +16,6 @@
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#ifndef __ARCH_ARM_MACH_OMAP2_CONTROL_H
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#define __ARCH_ARM_MACH_OMAP2_CONTROL_H
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#include "ctrl_module_core_44xx.h"
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#include "ctrl_module_wkup_44xx.h"
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#include "ctrl_module_pad_core_44xx.h"
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#include "ctrl_module_pad_wkup_44xx.h"
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#include "am33xx.h"
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#ifndef __ASSEMBLY__
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@ -254,6 +249,39 @@
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/* TI81XX CONTROL_DEVCONF register offsets */
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#define TI81XX_CONTROL_DEVICE_ID (TI81XX_CONTROL_DEVCONF + 0x000)
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/* OMAP4 CONTROL MODULE */
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#define OMAP4_CTRL_MODULE_PAD_WKUP 0x4a31e000
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#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_I2C_2 0x0604
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#define OMAP4_CTRL_MODULE_CORE_STATUS 0x02c4
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#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1 0x0218
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#define OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR 0x0304
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#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY 0x0618
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#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_CAMERA_RX 0x0608
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/* OMAP4 CONTROL_DSIPHY */
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#define OMAP4_DSI2_LANEENABLE_SHIFT 29
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#define OMAP4_DSI2_LANEENABLE_MASK (0x7 << 29)
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#define OMAP4_DSI1_LANEENABLE_SHIFT 24
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#define OMAP4_DSI1_LANEENABLE_MASK (0x1f << 24)
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#define OMAP4_DSI1_PIPD_SHIFT 19
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#define OMAP4_DSI1_PIPD_MASK (0x1f << 19)
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#define OMAP4_DSI2_PIPD_SHIFT 14
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#define OMAP4_DSI2_PIPD_MASK (0x1f << 14)
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/* OMAP4 CONTROL_CAMERA_RX */
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#define OMAP4_CAMERARX_CSI21_LANEENABLE_SHIFT 24
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#define OMAP4_CAMERARX_CSI21_LANEENABLE_MASK (0x1f << 24)
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#define OMAP4_CAMERARX_CSI22_LANEENABLE_SHIFT 29
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#define OMAP4_CAMERARX_CSI22_LANEENABLE_MASK (0x3 << 29)
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#define OMAP4_CAMERARX_CSI22_CTRLCLKEN_SHIFT 21
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#define OMAP4_CAMERARX_CSI22_CTRLCLKEN_MASK (1 << 21)
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#define OMAP4_CAMERARX_CSI22_CAMMODE_SHIFT 19
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#define OMAP4_CAMERARX_CSI22_CAMMODE_MASK (0x3 << 19)
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#define OMAP4_CAMERARX_CSI21_CTRLCLKEN_SHIFT 18
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#define OMAP4_CAMERARX_CSI21_CTRLCLKEN_MASK (1 << 18)
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#define OMAP4_CAMERARX_CSI21_CAMMODE_SHIFT 16
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#define OMAP4_CAMERARX_CSI21_CAMMODE_MASK (0x3 << 16)
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/* OMAP54XX CONTROL STATUS register */
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#define OMAP5XXX_CONTROL_STATUS 0x134
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#define OMAP5_DEVICETYPE_MASK (0x7 << 6)
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@ -1,392 +0,0 @@
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/*
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* OMAP44xx CTRL_MODULE_CORE registers and bitfields
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*
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* Copyright (C) 2009-2010 Texas Instruments, Inc.
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*
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* Benoit Cousson (b-cousson@ti.com)
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* Santosh Shilimkar (santosh.shilimkar@ti.com)
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*
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* This file is automatically generated from the OMAP hardware databases.
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* We respectfully ask that any modifications to this file be coordinated
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* with the public linux-omap@vger.kernel.org mailing list and the
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* authors above to ensure that the autogeneration scripts are kept
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* up-to-date with the file contents.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_CORE_44XX_H
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#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_CORE_44XX_H
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/* Base address */
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#define OMAP4_CTRL_MODULE_CORE 0x4a002000
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/* Registers offset */
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#define OMAP4_CTRL_MODULE_CORE_IP_REVISION 0x0000
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#define OMAP4_CTRL_MODULE_CORE_IP_HWINFO 0x0004
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#define OMAP4_CTRL_MODULE_CORE_IP_SYSCONFIG 0x0010
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#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_0 0x0200
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#define OMAP4_CTRL_MODULE_CORE_ID_CODE 0x0204
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#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_1 0x0208
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#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_2 0x020c
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#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_3 0x0210
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#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_0 0x0214
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#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1 0x0218
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#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_USB_CONF 0x021c
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#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_VDD_WKUP 0x0228
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#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_BGAP 0x0260
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#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_0 0x0264
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#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_1 0x0268
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#define OMAP4_CTRL_MODULE_CORE_STATUS 0x02c4
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#define OMAP4_CTRL_MODULE_CORE_DEV_CONF 0x0300
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#define OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR 0x0304
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#define OMAP4_CTRL_MODULE_CORE_LDOVBB_IVA_VOLTAGE_CTRL 0x0314
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#define OMAP4_CTRL_MODULE_CORE_LDOVBB_MPU_VOLTAGE_CTRL 0x0318
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#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_IVA_VOLTAGE_CTRL 0x0320
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#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_MPU_VOLTAGE_CTRL 0x0324
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#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_CORE_VOLTAGE_CTRL 0x0328
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#define OMAP4_CTRL_MODULE_CORE_TEMP_SENSOR 0x032c
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#define OMAP4_CTRL_MODULE_CORE_DPLL_NWELL_TRIM_0 0x0330
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#define OMAP4_CTRL_MODULE_CORE_DPLL_NWELL_TRIM_1 0x0334
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#define OMAP4_CTRL_MODULE_CORE_USBOTGHS_CONTROL 0x033c
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#define OMAP4_CTRL_MODULE_CORE_DSS_CONTROL 0x0340
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#define OMAP4_CTRL_MODULE_CORE_HWOBS_CONTROL 0x0350
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#define OMAP4_CTRL_MODULE_CORE_DEBOBS_FINAL_MUX_SEL 0x0400
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#define OMAP4_CTRL_MODULE_CORE_DEBOBS_MMR_MPU 0x0408
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#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL0 0x042c
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#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL1 0x0430
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#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL2 0x0434
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#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL3 0x0438
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#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL0 0x0440
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#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL1 0x0444
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#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL2 0x0448
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#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_FREQLOCK_SEL 0x044c
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#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_TINITZ_SEL 0x0450
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#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_PHASELOCK_SEL 0x0454
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#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_0 0x0480
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#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_1 0x0484
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#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_2 0x0488
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#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_3 0x048c
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#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_4 0x0490
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#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_5 0x0494
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#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_6 0x0498
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#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_7 0x049c
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#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_8 0x04a0
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#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_9 0x04a4
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#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_10 0x04a8
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#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_11 0x04ac
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#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_12 0x04b0
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#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_13 0x04b4
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#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_14 0x04b8
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#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_15 0x04bc
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#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_16 0x04c0
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#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_17 0x04c4
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#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_18 0x04c8
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#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_19 0x04cc
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#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_20 0x04d0
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#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_21 0x04d4
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#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_22 0x04d8
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#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_23 0x04dc
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#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_24 0x04e0
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#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_25 0x04e4
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#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_26 0x04e8
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#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_27 0x04ec
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#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_28 0x04f0
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#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_29 0x04f4
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#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_30 0x04f8
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#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_31 0x04fc
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/* Registers shifts and masks */
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/* IP_REVISION */
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#define OMAP4_IP_REV_SCHEME_SHIFT 30
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#define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30)
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#define OMAP4_IP_REV_FUNC_SHIFT 16
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#define OMAP4_IP_REV_FUNC_MASK (0xfff << 16)
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#define OMAP4_IP_REV_RTL_SHIFT 11
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#define OMAP4_IP_REV_RTL_MASK (0x1f << 11)
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#define OMAP4_IP_REV_MAJOR_SHIFT 8
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#define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8)
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#define OMAP4_IP_REV_CUSTOM_SHIFT 6
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#define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6)
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#define OMAP4_IP_REV_MINOR_SHIFT 0
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#define OMAP4_IP_REV_MINOR_MASK (0x3f << 0)
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/* IP_HWINFO */
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#define OMAP4_IP_HWINFO_SHIFT 0
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#define OMAP4_IP_HWINFO_MASK (0xffffffff << 0)
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/* IP_SYSCONFIG */
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#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2
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#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2)
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/* STD_FUSE_DIE_ID_0 */
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#define OMAP4_STD_FUSE_DIE_ID_0_SHIFT 0
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#define OMAP4_STD_FUSE_DIE_ID_0_MASK (0xffffffff << 0)
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/* ID_CODE */
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#define OMAP4_STD_FUSE_IDCODE_SHIFT 0
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#define OMAP4_STD_FUSE_IDCODE_MASK (0xffffffff << 0)
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/* STD_FUSE_DIE_ID_1 */
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#define OMAP4_STD_FUSE_DIE_ID_1_SHIFT 0
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#define OMAP4_STD_FUSE_DIE_ID_1_MASK (0xffffffff << 0)
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/* STD_FUSE_DIE_ID_2 */
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#define OMAP4_STD_FUSE_DIE_ID_2_SHIFT 0
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#define OMAP4_STD_FUSE_DIE_ID_2_MASK (0xffffffff << 0)
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/* STD_FUSE_DIE_ID_3 */
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#define OMAP4_STD_FUSE_DIE_ID_3_SHIFT 0
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#define OMAP4_STD_FUSE_DIE_ID_3_MASK (0xffffffff << 0)
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/* STD_FUSE_PROD_ID_0 */
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#define OMAP4_STD_FUSE_PROD_ID_0_SHIFT 0
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#define OMAP4_STD_FUSE_PROD_ID_0_MASK (0xffffffff << 0)
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/* STD_FUSE_PROD_ID_1 */
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#define OMAP4_STD_FUSE_PROD_ID_1_SHIFT 0
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#define OMAP4_STD_FUSE_PROD_ID_1_MASK (0xffffffff << 0)
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/* STD_FUSE_USB_CONF */
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#define OMAP4_USB_PROD_ID_SHIFT 16
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#define OMAP4_USB_PROD_ID_MASK (0xffff << 16)
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#define OMAP4_USB_VENDOR_ID_SHIFT 0
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#define OMAP4_USB_VENDOR_ID_MASK (0xffff << 0)
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/* STD_FUSE_OPP_VDD_WKUP */
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#define OMAP4_STD_FUSE_OPP_VDD_WKUP_SHIFT 0
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#define OMAP4_STD_FUSE_OPP_VDD_WKUP_MASK (0xffffffff << 0)
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/* STD_FUSE_OPP_BGAP */
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#define OMAP4_STD_FUSE_OPP_BGAP_SHIFT 0
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#define OMAP4_STD_FUSE_OPP_BGAP_MASK (0xffffffff << 0)
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/* STD_FUSE_OPP_DPLL_0 */
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#define OMAP4_STD_FUSE_OPP_DPLL_0_SHIFT 0
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#define OMAP4_STD_FUSE_OPP_DPLL_0_MASK (0xffffffff << 0)
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/* STD_FUSE_OPP_DPLL_1 */
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#define OMAP4_STD_FUSE_OPP_DPLL_1_SHIFT 0
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#define OMAP4_STD_FUSE_OPP_DPLL_1_MASK (0xffffffff << 0)
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/* STATUS */
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#define OMAP4_ATTILA_CONF_SHIFT 11
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#define OMAP4_ATTILA_CONF_MASK (0x3 << 11)
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#define OMAP4_DEVICE_TYPE_SHIFT 8
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#define OMAP4_DEVICE_TYPE_MASK (0x7 << 8)
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#define OMAP4_SYS_BOOT_SHIFT 0
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#define OMAP4_SYS_BOOT_MASK (0xff << 0)
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/* DEV_CONF */
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#define OMAP4_DEV_CONF_SHIFT 1
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#define OMAP4_DEV_CONF_MASK (0x7fffffff << 1)
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#define OMAP4_USBPHY_PD_SHIFT 0
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#define OMAP4_USBPHY_PD_MASK (1 << 0)
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/* LDOVBB_IVA_VOLTAGE_CTRL */
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#define OMAP4_LDOVBBIVA_RBB_MUX_CTRL_SHIFT 26
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#define OMAP4_LDOVBBIVA_RBB_MUX_CTRL_MASK (1 << 26)
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#define OMAP4_LDOVBBIVA_RBB_VSET_IN_SHIFT 21
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#define OMAP4_LDOVBBIVA_RBB_VSET_IN_MASK (0x1f << 21)
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#define OMAP4_LDOVBBIVA_RBB_VSET_OUT_SHIFT 16
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#define OMAP4_LDOVBBIVA_RBB_VSET_OUT_MASK (0x1f << 16)
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#define OMAP4_LDOVBBIVA_FBB_MUX_CTRL_SHIFT 10
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#define OMAP4_LDOVBBIVA_FBB_MUX_CTRL_MASK (1 << 10)
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#define OMAP4_LDOVBBIVA_FBB_VSET_IN_SHIFT 5
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#define OMAP4_LDOVBBIVA_FBB_VSET_IN_MASK (0x1f << 5)
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#define OMAP4_LDOVBBIVA_FBB_VSET_OUT_SHIFT 0
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#define OMAP4_LDOVBBIVA_FBB_VSET_OUT_MASK (0x1f << 0)
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/* LDOVBB_MPU_VOLTAGE_CTRL */
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#define OMAP4_LDOVBBMPU_RBB_MUX_CTRL_SHIFT 26
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#define OMAP4_LDOVBBMPU_RBB_MUX_CTRL_MASK (1 << 26)
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#define OMAP4_LDOVBBMPU_RBB_VSET_IN_SHIFT 21
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#define OMAP4_LDOVBBMPU_RBB_VSET_IN_MASK (0x1f << 21)
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#define OMAP4_LDOVBBMPU_RBB_VSET_OUT_SHIFT 16
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#define OMAP4_LDOVBBMPU_RBB_VSET_OUT_MASK (0x1f << 16)
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#define OMAP4_LDOVBBMPU_FBB_MUX_CTRL_SHIFT 10
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#define OMAP4_LDOVBBMPU_FBB_MUX_CTRL_MASK (1 << 10)
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#define OMAP4_LDOVBBMPU_FBB_VSET_IN_SHIFT 5
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#define OMAP4_LDOVBBMPU_FBB_VSET_IN_MASK (0x1f << 5)
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#define OMAP4_LDOVBBMPU_FBB_VSET_OUT_SHIFT 0
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#define OMAP4_LDOVBBMPU_FBB_VSET_OUT_MASK (0x1f << 0)
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/* LDOSRAM_IVA_VOLTAGE_CTRL */
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#define OMAP4_LDOSRAMIVA_RETMODE_MUX_CTRL_SHIFT 26
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#define OMAP4_LDOSRAMIVA_RETMODE_MUX_CTRL_MASK (1 << 26)
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#define OMAP4_LDOSRAMIVA_RETMODE_VSET_IN_SHIFT 21
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#define OMAP4_LDOSRAMIVA_RETMODE_VSET_IN_MASK (0x1f << 21)
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#define OMAP4_LDOSRAMIVA_RETMODE_VSET_OUT_SHIFT 16
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#define OMAP4_LDOSRAMIVA_RETMODE_VSET_OUT_MASK (0x1f << 16)
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#define OMAP4_LDOSRAMIVA_ACTMODE_MUX_CTRL_SHIFT 10
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#define OMAP4_LDOSRAMIVA_ACTMODE_MUX_CTRL_MASK (1 << 10)
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#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_IN_SHIFT 5
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#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_IN_MASK (0x1f << 5)
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#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_OUT_SHIFT 0
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#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_OUT_MASK (0x1f << 0)
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/* LDOSRAM_MPU_VOLTAGE_CTRL */
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#define OMAP4_LDOSRAMMPU_RETMODE_MUX_CTRL_SHIFT 26
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#define OMAP4_LDOSRAMMPU_RETMODE_MUX_CTRL_MASK (1 << 26)
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#define OMAP4_LDOSRAMMPU_RETMODE_VSET_IN_SHIFT 21
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#define OMAP4_LDOSRAMMPU_RETMODE_VSET_IN_MASK (0x1f << 21)
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#define OMAP4_LDOSRAMMPU_RETMODE_VSET_OUT_SHIFT 16
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#define OMAP4_LDOSRAMMPU_RETMODE_VSET_OUT_MASK (0x1f << 16)
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#define OMAP4_LDOSRAMMPU_ACTMODE_MUX_CTRL_SHIFT 10
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#define OMAP4_LDOSRAMMPU_ACTMODE_MUX_CTRL_MASK (1 << 10)
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#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_IN_SHIFT 5
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#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_IN_MASK (0x1f << 5)
|
||||
#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_OUT_SHIFT 0
|
||||
#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_OUT_MASK (0x1f << 0)
|
||||
|
||||
/* LDOSRAM_CORE_VOLTAGE_CTRL */
|
||||
#define OMAP4_LDOSRAMCORE_RETMODE_MUX_CTRL_SHIFT 26
|
||||
#define OMAP4_LDOSRAMCORE_RETMODE_MUX_CTRL_MASK (1 << 26)
|
||||
#define OMAP4_LDOSRAMCORE_RETMODE_VSET_IN_SHIFT 21
|
||||
#define OMAP4_LDOSRAMCORE_RETMODE_VSET_IN_MASK (0x1f << 21)
|
||||
#define OMAP4_LDOSRAMCORE_RETMODE_VSET_OUT_SHIFT 16
|
||||
#define OMAP4_LDOSRAMCORE_RETMODE_VSET_OUT_MASK (0x1f << 16)
|
||||
#define OMAP4_LDOSRAMCORE_ACTMODE_MUX_CTRL_SHIFT 10
|
||||
#define OMAP4_LDOSRAMCORE_ACTMODE_MUX_CTRL_MASK (1 << 10)
|
||||
#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_IN_SHIFT 5
|
||||
#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_IN_MASK (0x1f << 5)
|
||||
#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_OUT_SHIFT 0
|
||||
#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_OUT_MASK (0x1f << 0)
|
||||
|
||||
/* TEMP_SENSOR */
|
||||
#define OMAP4_BGAP_TEMPSOFF_SHIFT 12
|
||||
#define OMAP4_BGAP_TEMPSOFF_MASK (1 << 12)
|
||||
#define OMAP4_BGAP_TSHUT_SHIFT 11
|
||||
#define OMAP4_BGAP_TSHUT_MASK (1 << 11)
|
||||
#define OMAP4_BGAP_TEMP_SENSOR_CONTCONV_SHIFT 10
|
||||
#define OMAP4_BGAP_TEMP_SENSOR_CONTCONV_MASK (1 << 10)
|
||||
#define OMAP4_BGAP_TEMP_SENSOR_SOC_SHIFT 9
|
||||
#define OMAP4_BGAP_TEMP_SENSOR_SOC_MASK (1 << 9)
|
||||
#define OMAP4_BGAP_TEMP_SENSOR_EOCZ_SHIFT 8
|
||||
#define OMAP4_BGAP_TEMP_SENSOR_EOCZ_MASK (1 << 8)
|
||||
#define OMAP4_BGAP_TEMP_SENSOR_DTEMP_SHIFT 0
|
||||
#define OMAP4_BGAP_TEMP_SENSOR_DTEMP_MASK (0xff << 0)
|
||||
|
||||
/* DPLL_NWELL_TRIM_0 */
|
||||
#define OMAP4_DPLL_ABE_NWELL_TRIM_MUX_CTRL_SHIFT 29
|
||||
#define OMAP4_DPLL_ABE_NWELL_TRIM_MUX_CTRL_MASK (1 << 29)
|
||||
#define OMAP4_DPLL_ABE_NWELL_TRIM_SHIFT 24
|
||||
#define OMAP4_DPLL_ABE_NWELL_TRIM_MASK (0x1f << 24)
|
||||
#define OMAP4_DPLL_PER_NWELL_TRIM_MUX_CTRL_SHIFT 23
|
||||
#define OMAP4_DPLL_PER_NWELL_TRIM_MUX_CTRL_MASK (1 << 23)
|
||||
#define OMAP4_DPLL_PER_NWELL_TRIM_SHIFT 18
|
||||
#define OMAP4_DPLL_PER_NWELL_TRIM_MASK (0x1f << 18)
|
||||
#define OMAP4_DPLL_CORE_NWELL_TRIM_MUX_CTRL_SHIFT 17
|
||||
#define OMAP4_DPLL_CORE_NWELL_TRIM_MUX_CTRL_MASK (1 << 17)
|
||||
#define OMAP4_DPLL_CORE_NWELL_TRIM_SHIFT 12
|
||||
#define OMAP4_DPLL_CORE_NWELL_TRIM_MASK (0x1f << 12)
|
||||
#define OMAP4_DPLL_IVA_NWELL_TRIM_MUX_CTRL_SHIFT 11
|
||||
#define OMAP4_DPLL_IVA_NWELL_TRIM_MUX_CTRL_MASK (1 << 11)
|
||||
#define OMAP4_DPLL_IVA_NWELL_TRIM_SHIFT 6
|
||||
#define OMAP4_DPLL_IVA_NWELL_TRIM_MASK (0x1f << 6)
|
||||
#define OMAP4_DPLL_MPU_NWELL_TRIM_MUX_CTRL_SHIFT 5
|
||||
#define OMAP4_DPLL_MPU_NWELL_TRIM_MUX_CTRL_MASK (1 << 5)
|
||||
#define OMAP4_DPLL_MPU_NWELL_TRIM_SHIFT 0
|
||||
#define OMAP4_DPLL_MPU_NWELL_TRIM_MASK (0x1f << 0)
|
||||
|
||||
/* DPLL_NWELL_TRIM_1 */
|
||||
#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MUX_CTRL_SHIFT 29
|
||||
#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MUX_CTRL_MASK (1 << 29)
|
||||
#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_SHIFT 24
|
||||
#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MASK (0x1f << 24)
|
||||
#define OMAP4_DPLL_USB_NWELL_TRIM_MUX_CTRL_SHIFT 23
|
||||
#define OMAP4_DPLL_USB_NWELL_TRIM_MUX_CTRL_MASK (1 << 23)
|
||||
#define OMAP4_DPLL_USB_NWELL_TRIM_SHIFT 18
|
||||
#define OMAP4_DPLL_USB_NWELL_TRIM_MASK (0x1f << 18)
|
||||
#define OMAP4_DPLL_HDMI_NWELL_TRIM_MUX_CTRL_SHIFT 17
|
||||
#define OMAP4_DPLL_HDMI_NWELL_TRIM_MUX_CTRL_MASK (1 << 17)
|
||||
#define OMAP4_DPLL_HDMI_NWELL_TRIM_SHIFT 12
|
||||
#define OMAP4_DPLL_HDMI_NWELL_TRIM_MASK (0x1f << 12)
|
||||
#define OMAP4_DPLL_DSI2_NWELL_TRIM_MUX_CTRL_SHIFT 11
|
||||
#define OMAP4_DPLL_DSI2_NWELL_TRIM_MUX_CTRL_MASK (1 << 11)
|
||||
#define OMAP4_DPLL_DSI2_NWELL_TRIM_SHIFT 6
|
||||
#define OMAP4_DPLL_DSI2_NWELL_TRIM_MASK (0x1f << 6)
|
||||
#define OMAP4_DPLL_DSI1_NWELL_TRIM_MUX_CTRL_SHIFT 5
|
||||
#define OMAP4_DPLL_DSI1_NWELL_TRIM_MUX_CTRL_MASK (1 << 5)
|
||||
#define OMAP4_DPLL_DSI1_NWELL_TRIM_SHIFT 0
|
||||
#define OMAP4_DPLL_DSI1_NWELL_TRIM_MASK (0x1f << 0)
|
||||
|
||||
/* USBOTGHS_CONTROL */
|
||||
#define OMAP4_DISCHRGVBUS_SHIFT 8
|
||||
#define OMAP4_DISCHRGVBUS_MASK (1 << 8)
|
||||
#define OMAP4_CHRGVBUS_SHIFT 7
|
||||
#define OMAP4_CHRGVBUS_MASK (1 << 7)
|
||||
#define OMAP4_DRVVBUS_SHIFT 6
|
||||
#define OMAP4_DRVVBUS_MASK (1 << 6)
|
||||
#define OMAP4_IDPULLUP_SHIFT 5
|
||||
#define OMAP4_IDPULLUP_MASK (1 << 5)
|
||||
#define OMAP4_IDDIG_SHIFT 4
|
||||
#define OMAP4_IDDIG_MASK (1 << 4)
|
||||
#define OMAP4_SESSEND_SHIFT 3
|
||||
#define OMAP4_SESSEND_MASK (1 << 3)
|
||||
#define OMAP4_VBUSVALID_SHIFT 2
|
||||
#define OMAP4_VBUSVALID_MASK (1 << 2)
|
||||
#define OMAP4_BVALID_SHIFT 1
|
||||
#define OMAP4_BVALID_MASK (1 << 1)
|
||||
#define OMAP4_AVALID_SHIFT 0
|
||||
#define OMAP4_AVALID_MASK (1 << 0)
|
||||
|
||||
/* DSS_CONTROL */
|
||||
#define OMAP4_DSS_MUX6_SELECT_SHIFT 0
|
||||
#define OMAP4_DSS_MUX6_SELECT_MASK (1 << 0)
|
||||
|
||||
/* HWOBS_CONTROL */
|
||||
#define OMAP4_HWOBS_CLKDIV_SEL_SHIFT 3
|
||||
#define OMAP4_HWOBS_CLKDIV_SEL_MASK (0x1f << 3)
|
||||
#define OMAP4_HWOBS_ALL_ZERO_MODE_SHIFT 2
|
||||
#define OMAP4_HWOBS_ALL_ZERO_MODE_MASK (1 << 2)
|
||||
#define OMAP4_HWOBS_ALL_ONE_MODE_SHIFT 1
|
||||
#define OMAP4_HWOBS_ALL_ONE_MODE_MASK (1 << 1)
|
||||
#define OMAP4_HWOBS_MACRO_ENABLE_SHIFT 0
|
||||
#define OMAP4_HWOBS_MACRO_ENABLE_MASK (1 << 0)
|
||||
|
||||
/* DEBOBS_FINAL_MUX_SEL */
|
||||
#define OMAP4_SELECT_SHIFT 0
|
||||
#define OMAP4_SELECT_MASK (0xffffffff << 0)
|
||||
|
||||
/* DEBOBS_MMR_MPU */
|
||||
#define OMAP4_SELECT_DEBOBS_MMR_MPU_SHIFT 0
|
||||
#define OMAP4_SELECT_DEBOBS_MMR_MPU_MASK (0xf << 0)
|
||||
|
||||
/* CONF_SDMA_REQ_SEL0 */
|
||||
#define OMAP4_MULT_SHIFT 0
|
||||
#define OMAP4_MULT_MASK (0x7f << 0)
|
||||
|
||||
/* CONF_CLK_SEL0 */
|
||||
#define OMAP4_MULT_CONF_CLK_SEL0_SHIFT 0
|
||||
#define OMAP4_MULT_CONF_CLK_SEL0_MASK (0x7 << 0)
|
||||
|
||||
/* CONF_CLK_SEL1 */
|
||||
#define OMAP4_MULT_CONF_CLK_SEL1_SHIFT 0
|
||||
#define OMAP4_MULT_CONF_CLK_SEL1_MASK (0x7 << 0)
|
||||
|
||||
/* CONF_CLK_SEL2 */
|
||||
#define OMAP4_MULT_CONF_CLK_SEL2_SHIFT 0
|
||||
#define OMAP4_MULT_CONF_CLK_SEL2_MASK (0x7 << 0)
|
||||
|
||||
/* CONF_DPLL_FREQLOCK_SEL */
|
||||
#define OMAP4_MULT_CONF_DPLL_FREQLOCK_SEL_SHIFT 0
|
||||
#define OMAP4_MULT_CONF_DPLL_FREQLOCK_SEL_MASK (0x7 << 0)
|
||||
|
||||
/* CONF_DPLL_TINITZ_SEL */
|
||||
#define OMAP4_MULT_CONF_DPLL_TINITZ_SEL_SHIFT 0
|
||||
#define OMAP4_MULT_CONF_DPLL_TINITZ_SEL_MASK (0x7 << 0)
|
||||
|
||||
/* CONF_DPLL_PHASELOCK_SEL */
|
||||
#define OMAP4_MULT_CONF_DPLL_PHASELOCK_SEL_SHIFT 0
|
||||
#define OMAP4_MULT_CONF_DPLL_PHASELOCK_SEL_MASK (0x7 << 0)
|
||||
|
||||
/* CONF_DEBUG_SEL_TST_0 */
|
||||
#define OMAP4_MODE_SHIFT 0
|
||||
#define OMAP4_MODE_MASK (0xf << 0)
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,236 +0,0 @@
|
||||
/*
|
||||
* OMAP44xx CTRL_MODULE_PAD_WKUP registers and bitfields
|
||||
*
|
||||
* Copyright (C) 2009-2010 Texas Instruments, Inc.
|
||||
*
|
||||
* Benoit Cousson (b-cousson@ti.com)
|
||||
* Santosh Shilimkar (santosh.shilimkar@ti.com)
|
||||
*
|
||||
* This file is automatically generated from the OMAP hardware databases.
|
||||
* We respectfully ask that any modifications to this file be coordinated
|
||||
* with the public linux-omap@vger.kernel.org mailing list and the
|
||||
* authors above to ensure that the autogeneration scripts are kept
|
||||
* up-to-date with the file contents.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_WKUP_44XX_H
|
||||
#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_WKUP_44XX_H
|
||||
|
||||
|
||||
/* Base address */
|
||||
#define OMAP4_CTRL_MODULE_PAD_WKUP 0x4a31e000
|
||||
|
||||
/* Registers offset */
|
||||
#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_REVISION 0x0000
|
||||
#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_HWINFO 0x0004
|
||||
#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_SYSCONFIG 0x0010
|
||||
#define OMAP4_CTRL_MODULE_PAD_WKUP_PADCONF_WAKEUPEVENT_0 0x007c
|
||||
#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SMART1NOPMIO_PADCONF_0 0x05a0
|
||||
#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SMART1NOPMIO_PADCONF_1 0x05a4
|
||||
#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_PADCONF_MODE 0x05a8
|
||||
#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_XTAL_OSCILLATOR 0x05ac
|
||||
#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_USIMIO 0x0600
|
||||
#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_I2C_2 0x0604
|
||||
#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_JTAG 0x0608
|
||||
#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SYS 0x060c
|
||||
#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_RW 0x0614
|
||||
#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_R 0x0618
|
||||
#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_R_C0 0x061c
|
||||
|
||||
/* Registers shifts and masks */
|
||||
|
||||
/* IP_REVISION */
|
||||
#define OMAP4_IP_REV_SCHEME_SHIFT 30
|
||||
#define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30)
|
||||
#define OMAP4_IP_REV_FUNC_SHIFT 16
|
||||
#define OMAP4_IP_REV_FUNC_MASK (0xfff << 16)
|
||||
#define OMAP4_IP_REV_RTL_SHIFT 11
|
||||
#define OMAP4_IP_REV_RTL_MASK (0x1f << 11)
|
||||
#define OMAP4_IP_REV_MAJOR_SHIFT 8
|
||||
#define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8)
|
||||
#define OMAP4_IP_REV_CUSTOM_SHIFT 6
|
||||
#define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6)
|
||||
#define OMAP4_IP_REV_MINOR_SHIFT 0
|
||||
#define OMAP4_IP_REV_MINOR_MASK (0x3f << 0)
|
||||
|
||||
/* IP_HWINFO */
|
||||
#define OMAP4_IP_HWINFO_SHIFT 0
|
||||
#define OMAP4_IP_HWINFO_MASK (0xffffffff << 0)
|
||||
|
||||
/* IP_SYSCONFIG */
|
||||
#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2
|
||||
#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2)
|
||||
|
||||
/* PADCONF_WAKEUPEVENT_0 */
|
||||
#define OMAP4_JTAG_TDO_DUPLICATEWAKEUPEVENT_SHIFT 24
|
||||
#define OMAP4_JTAG_TDO_DUPLICATEWAKEUPEVENT_MASK (1 << 24)
|
||||
#define OMAP4_JTAG_TDI_DUPLICATEWAKEUPEVENT_SHIFT 23
|
||||
#define OMAP4_JTAG_TDI_DUPLICATEWAKEUPEVENT_MASK (1 << 23)
|
||||
#define OMAP4_JTAG_TMS_TMSC_DUPLICATEWAKEUPEVENT_SHIFT 22
|
||||
#define OMAP4_JTAG_TMS_TMSC_DUPLICATEWAKEUPEVENT_MASK (1 << 22)
|
||||
#define OMAP4_JTAG_RTCK_DUPLICATEWAKEUPEVENT_SHIFT 21
|
||||
#define OMAP4_JTAG_RTCK_DUPLICATEWAKEUPEVENT_MASK (1 << 21)
|
||||
#define OMAP4_JTAG_TCK_DUPLICATEWAKEUPEVENT_SHIFT 20
|
||||
#define OMAP4_JTAG_TCK_DUPLICATEWAKEUPEVENT_MASK (1 << 20)
|
||||
#define OMAP4_JTAG_NTRST_DUPLICATEWAKEUPEVENT_SHIFT 19
|
||||
#define OMAP4_JTAG_NTRST_DUPLICATEWAKEUPEVENT_MASK (1 << 19)
|
||||
#define OMAP4_SYS_BOOT7_DUPLICATEWAKEUPEVENT_SHIFT 18
|
||||
#define OMAP4_SYS_BOOT7_DUPLICATEWAKEUPEVENT_MASK (1 << 18)
|
||||
#define OMAP4_SYS_BOOT6_DUPLICATEWAKEUPEVENT_SHIFT 17
|
||||
#define OMAP4_SYS_BOOT6_DUPLICATEWAKEUPEVENT_MASK (1 << 17)
|
||||
#define OMAP4_SYS_PWRON_RESET_OUT_DUPLICATEWAKEUPEVENT_SHIFT 16
|
||||
#define OMAP4_SYS_PWRON_RESET_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 16)
|
||||
#define OMAP4_SYS_PWR_REQ_DUPLICATEWAKEUPEVENT_SHIFT 15
|
||||
#define OMAP4_SYS_PWR_REQ_DUPLICATEWAKEUPEVENT_MASK (1 << 15)
|
||||
#define OMAP4_SYS_NRESWARM_DUPLICATEWAKEUPEVENT_SHIFT 14
|
||||
#define OMAP4_SYS_NRESWARM_DUPLICATEWAKEUPEVENT_MASK (1 << 14)
|
||||
#define OMAP4_SYS_32K_DUPLICATEWAKEUPEVENT_SHIFT 13
|
||||
#define OMAP4_SYS_32K_DUPLICATEWAKEUPEVENT_MASK (1 << 13)
|
||||
#define OMAP4_FREF_CLK4_OUT_DUPLICATEWAKEUPEVENT_SHIFT 12
|
||||
#define OMAP4_FREF_CLK4_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 12)
|
||||
#define OMAP4_FREF_CLK4_REQ_DUPLICATEWAKEUPEVENT_SHIFT 11
|
||||
#define OMAP4_FREF_CLK4_REQ_DUPLICATEWAKEUPEVENT_MASK (1 << 11)
|
||||
#define OMAP4_FREF_CLK3_OUT_DUPLICATEWAKEUPEVENT_SHIFT 10
|
||||
#define OMAP4_FREF_CLK3_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 10)
|
||||
#define OMAP4_FREF_CLK3_REQ_DUPLICATEWAKEUPEVENT_SHIFT 9
|
||||
#define OMAP4_FREF_CLK3_REQ_DUPLICATEWAKEUPEVENT_MASK (1 << 9)
|
||||
#define OMAP4_FREF_CLK0_OUT_DUPLICATEWAKEUPEVENT_SHIFT 8
|
||||
#define OMAP4_FREF_CLK0_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 8)
|
||||
#define OMAP4_FREF_CLK_IOREQ_DUPLICATEWAKEUPEVENT_SHIFT 7
|
||||
#define OMAP4_FREF_CLK_IOREQ_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
|
||||
#define OMAP4_SR_SDA_DUPLICATEWAKEUPEVENT_SHIFT 6
|
||||
#define OMAP4_SR_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
|
||||
#define OMAP4_SR_SCL_DUPLICATEWAKEUPEVENT_SHIFT 5
|
||||
#define OMAP4_SR_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
|
||||
#define OMAP4_SIM_PWRCTRL_DUPLICATEWAKEUPEVENT_SHIFT 4
|
||||
#define OMAP4_SIM_PWRCTRL_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
|
||||
#define OMAP4_SIM_CD_DUPLICATEWAKEUPEVENT_SHIFT 3
|
||||
#define OMAP4_SIM_CD_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
|
||||
#define OMAP4_SIM_RESET_DUPLICATEWAKEUPEVENT_SHIFT 2
|
||||
#define OMAP4_SIM_RESET_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
|
||||
#define OMAP4_SIM_CLK_DUPLICATEWAKEUPEVENT_SHIFT 1
|
||||
#define OMAP4_SIM_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
|
||||
#define OMAP4_SIM_IO_DUPLICATEWAKEUPEVENT_SHIFT 0
|
||||
#define OMAP4_SIM_IO_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
|
||||
|
||||
/* CONTROL_SMART1NOPMIO_PADCONF_0 */
|
||||
#define OMAP4_FREF_DR0_SC_SHIFT 30
|
||||
#define OMAP4_FREF_DR0_SC_MASK (0x3 << 30)
|
||||
#define OMAP4_FREF_DR1_SC_SHIFT 28
|
||||
#define OMAP4_FREF_DR1_SC_MASK (0x3 << 28)
|
||||
#define OMAP4_FREF_DR4_SC_SHIFT 26
|
||||
#define OMAP4_FREF_DR4_SC_MASK (0x3 << 26)
|
||||
#define OMAP4_FREF_DR5_SC_SHIFT 24
|
||||
#define OMAP4_FREF_DR5_SC_MASK (0x3 << 24)
|
||||
#define OMAP4_FREF_DR6_SC_SHIFT 22
|
||||
#define OMAP4_FREF_DR6_SC_MASK (0x3 << 22)
|
||||
#define OMAP4_FREF_DR7_SC_SHIFT 20
|
||||
#define OMAP4_FREF_DR7_SC_MASK (0x3 << 20)
|
||||
#define OMAP4_GPIO_DR7_SC_SHIFT 18
|
||||
#define OMAP4_GPIO_DR7_SC_MASK (0x3 << 18)
|
||||
#define OMAP4_DPM_DR0_SC_SHIFT 14
|
||||
#define OMAP4_DPM_DR0_SC_MASK (0x3 << 14)
|
||||
#define OMAP4_SIM_DR0_SC_SHIFT 12
|
||||
#define OMAP4_SIM_DR0_SC_MASK (0x3 << 12)
|
||||
|
||||
/* CONTROL_SMART1NOPMIO_PADCONF_1 */
|
||||
#define OMAP4_FREF_DR0_LB_SHIFT 30
|
||||
#define OMAP4_FREF_DR0_LB_MASK (0x3 << 30)
|
||||
#define OMAP4_FREF_DR1_LB_SHIFT 28
|
||||
#define OMAP4_FREF_DR1_LB_MASK (0x3 << 28)
|
||||
#define OMAP4_FREF_DR4_LB_SHIFT 26
|
||||
#define OMAP4_FREF_DR4_LB_MASK (0x3 << 26)
|
||||
#define OMAP4_FREF_DR5_LB_SHIFT 24
|
||||
#define OMAP4_FREF_DR5_LB_MASK (0x3 << 24)
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#define OMAP4_FREF_DR6_LB_SHIFT 22
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#define OMAP4_FREF_DR6_LB_MASK (0x3 << 22)
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#define OMAP4_FREF_DR7_LB_SHIFT 20
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#define OMAP4_FREF_DR7_LB_MASK (0x3 << 20)
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||||
#define OMAP4_GPIO_DR7_LB_SHIFT 18
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#define OMAP4_GPIO_DR7_LB_MASK (0x3 << 18)
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#define OMAP4_DPM_DR0_LB_SHIFT 14
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||||
#define OMAP4_DPM_DR0_LB_MASK (0x3 << 14)
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#define OMAP4_SIM_DR0_LB_SHIFT 12
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||||
#define OMAP4_SIM_DR0_LB_MASK (0x3 << 12)
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||||
|
||||
/* CONTROL_PADCONF_MODE */
|
||||
#define OMAP4_VDDS_DV_FREF_SHIFT 31
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||||
#define OMAP4_VDDS_DV_FREF_MASK (1 << 31)
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||||
#define OMAP4_VDDS_DV_BANK2_SHIFT 30
|
||||
#define OMAP4_VDDS_DV_BANK2_MASK (1 << 30)
|
||||
|
||||
/* CONTROL_XTAL_OSCILLATOR */
|
||||
#define OMAP4_OSCILLATOR_BOOST_SHIFT 31
|
||||
#define OMAP4_OSCILLATOR_BOOST_MASK (1 << 31)
|
||||
#define OMAP4_OSCILLATOR_OS_OUT_SHIFT 30
|
||||
#define OMAP4_OSCILLATOR_OS_OUT_MASK (1 << 30)
|
||||
|
||||
/* CONTROL_USIMIO */
|
||||
#define OMAP4_PAD_USIM_CLK_LOW_SHIFT 31
|
||||
#define OMAP4_PAD_USIM_CLK_LOW_MASK (1 << 31)
|
||||
#define OMAP4_PAD_USIM_RST_LOW_SHIFT 29
|
||||
#define OMAP4_PAD_USIM_RST_LOW_MASK (1 << 29)
|
||||
#define OMAP4_USIM_PWRDNZ_SHIFT 28
|
||||
#define OMAP4_USIM_PWRDNZ_MASK (1 << 28)
|
||||
|
||||
/* CONTROL_I2C_2 */
|
||||
#define OMAP4_SR_SDA_GLFENB_SHIFT 31
|
||||
#define OMAP4_SR_SDA_GLFENB_MASK (1 << 31)
|
||||
#define OMAP4_SR_SDA_LOAD_BITS_SHIFT 29
|
||||
#define OMAP4_SR_SDA_LOAD_BITS_MASK (0x3 << 29)
|
||||
#define OMAP4_SR_SDA_PULLUPRESX_SHIFT 28
|
||||
#define OMAP4_SR_SDA_PULLUPRESX_MASK (1 << 28)
|
||||
#define OMAP4_SR_SCL_GLFENB_SHIFT 27
|
||||
#define OMAP4_SR_SCL_GLFENB_MASK (1 << 27)
|
||||
#define OMAP4_SR_SCL_LOAD_BITS_SHIFT 25
|
||||
#define OMAP4_SR_SCL_LOAD_BITS_MASK (0x3 << 25)
|
||||
#define OMAP4_SR_SCL_PULLUPRESX_SHIFT 24
|
||||
#define OMAP4_SR_SCL_PULLUPRESX_MASK (1 << 24)
|
||||
|
||||
/* CONTROL_JTAG */
|
||||
#define OMAP4_JTAG_NTRST_EN_SHIFT 31
|
||||
#define OMAP4_JTAG_NTRST_EN_MASK (1 << 31)
|
||||
#define OMAP4_JTAG_TCK_EN_SHIFT 30
|
||||
#define OMAP4_JTAG_TCK_EN_MASK (1 << 30)
|
||||
#define OMAP4_JTAG_RTCK_EN_SHIFT 29
|
||||
#define OMAP4_JTAG_RTCK_EN_MASK (1 << 29)
|
||||
#define OMAP4_JTAG_TDI_EN_SHIFT 28
|
||||
#define OMAP4_JTAG_TDI_EN_MASK (1 << 28)
|
||||
#define OMAP4_JTAG_TDO_EN_SHIFT 27
|
||||
#define OMAP4_JTAG_TDO_EN_MASK (1 << 27)
|
||||
|
||||
/* CONTROL_SYS */
|
||||
#define OMAP4_SYS_NRESWARM_PIPU_SHIFT 31
|
||||
#define OMAP4_SYS_NRESWARM_PIPU_MASK (1 << 31)
|
||||
|
||||
/* WKUP_CONTROL_SPARE_RW */
|
||||
#define OMAP4_WKUP_CONTROL_SPARE_RW_SHIFT 0
|
||||
#define OMAP4_WKUP_CONTROL_SPARE_RW_MASK (0xffffffff << 0)
|
||||
|
||||
/* WKUP_CONTROL_SPARE_R */
|
||||
#define OMAP4_WKUP_CONTROL_SPARE_R_SHIFT 0
|
||||
#define OMAP4_WKUP_CONTROL_SPARE_R_MASK (0xffffffff << 0)
|
||||
|
||||
/* WKUP_CONTROL_SPARE_R_C0 */
|
||||
#define OMAP4_WKUP_CONTROL_SPARE_R_C0_SHIFT 31
|
||||
#define OMAP4_WKUP_CONTROL_SPARE_R_C0_MASK (1 << 31)
|
||||
#define OMAP4_WKUP_CONTROL_SPARE_R_C1_SHIFT 30
|
||||
#define OMAP4_WKUP_CONTROL_SPARE_R_C1_MASK (1 << 30)
|
||||
#define OMAP4_WKUP_CONTROL_SPARE_R_C2_SHIFT 29
|
||||
#define OMAP4_WKUP_CONTROL_SPARE_R_C2_MASK (1 << 29)
|
||||
#define OMAP4_WKUP_CONTROL_SPARE_R_C3_SHIFT 28
|
||||
#define OMAP4_WKUP_CONTROL_SPARE_R_C3_MASK (1 << 28)
|
||||
#define OMAP4_WKUP_CONTROL_SPARE_R_C4_SHIFT 27
|
||||
#define OMAP4_WKUP_CONTROL_SPARE_R_C4_MASK (1 << 27)
|
||||
#define OMAP4_WKUP_CONTROL_SPARE_R_C5_SHIFT 26
|
||||
#define OMAP4_WKUP_CONTROL_SPARE_R_C5_MASK (1 << 26)
|
||||
#define OMAP4_WKUP_CONTROL_SPARE_R_C6_SHIFT 25
|
||||
#define OMAP4_WKUP_CONTROL_SPARE_R_C6_MASK (1 << 25)
|
||||
#define OMAP4_WKUP_CONTROL_SPARE_R_C7_SHIFT 24
|
||||
#define OMAP4_WKUP_CONTROL_SPARE_R_C7_MASK (1 << 24)
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user