forked from Minki/linux
drm/amdgpu: fix vulkan test performance drop and hang on VI
caused by not program dynamic_cu_mask_addr in the KIQ MQD. v2: create struct vi_mqd_allocation in FB which will contain 1. PM4 MQD structure. 2. Write Pointer Poll Memory. 3. Read Pointer Report Memory 4. Dynamic CU Mask. 5. Dynamic RB Mask. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Rex Zhu
Alex Deucher
parent
12d016626f
commit
6b0fa871a9
@ -40,7 +40,6 @@
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#include "bif/bif_5_0_d.h"
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#include "bif/bif_5_0_sh_mask.h"
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#include "gca/gfx_8_0_d.h"
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#include "gca/gfx_8_0_enum.h"
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#include "gca/gfx_8_0_sh_mask.h"
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@ -2100,7 +2099,7 @@ static int gfx_v8_0_sw_init(void *handle)
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return r;
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/* create MQD for all compute queues as well as KIQ for SRIOV case */
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r = amdgpu_gfx_compute_mqd_sw_init(adev, sizeof(struct vi_mqd));
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r = amdgpu_gfx_compute_mqd_sw_init(adev, sizeof(struct vi_mqd_allocation));
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if (r)
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return r;
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@ -4715,9 +4714,6 @@ static int gfx_v8_0_mqd_init(struct amdgpu_ring *ring)
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uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
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uint32_t tmp;
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/* init the mqd struct */
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memset(mqd, 0, sizeof(struct vi_mqd));
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mqd->header = 0xC0310800;
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mqd->compute_pipelinestat_enable = 0x00000001;
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mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
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@ -4725,7 +4721,12 @@ static int gfx_v8_0_mqd_init(struct amdgpu_ring *ring)
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mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
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mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
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mqd->compute_misc_reserved = 0x00000003;
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if (!(adev->flags & AMD_IS_APU)) {
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mqd->dynamic_cu_mask_addr_lo = lower_32_bits(ring->mqd_gpu_addr
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+ offsetof(struct vi_mqd_allocation, dyamic_cu_mask));
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mqd->dynamic_cu_mask_addr_hi = upper_32_bits(ring->mqd_gpu_addr
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+ offsetof(struct vi_mqd_allocation, dyamic_cu_mask));
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}
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eop_base_addr = ring->eop_gpu_addr >> 8;
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mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
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mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
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@ -4900,7 +4901,7 @@ static int gfx_v8_0_kiq_init_queue(struct amdgpu_ring *ring)
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if (adev->gfx.in_reset) { /* for GPU_RESET case */
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/* reset MQD to a clean status */
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if (adev->gfx.mec.mqd_backup[mqd_idx])
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memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
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memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct vi_mqd_allocation));
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/* reset ring buffer */
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ring->wptr = 0;
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@ -4916,6 +4917,9 @@ static int gfx_v8_0_kiq_init_queue(struct amdgpu_ring *ring)
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vi_srbm_select(adev, 0, 0, 0, 0);
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mutex_unlock(&adev->srbm_mutex);
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} else {
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memset((void *)mqd, 0, sizeof(struct vi_mqd_allocation));
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((struct vi_mqd_allocation *)mqd)->dyamic_cu_mask = 0xFFFFFFFF;
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((struct vi_mqd_allocation *)mqd)->dyamic_rb_mask = 0xFFFFFFFF;
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mutex_lock(&adev->srbm_mutex);
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vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
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gfx_v8_0_mqd_init(ring);
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@ -4929,7 +4933,7 @@ static int gfx_v8_0_kiq_init_queue(struct amdgpu_ring *ring)
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mutex_unlock(&adev->srbm_mutex);
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if (adev->gfx.mec.mqd_backup[mqd_idx])
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memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
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memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct vi_mqd_allocation));
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}
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return r;
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@ -4947,6 +4951,9 @@ static int gfx_v8_0_kcq_init_queue(struct amdgpu_ring *ring)
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int mqd_idx = ring - &adev->gfx.compute_ring[0];
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if (!adev->gfx.in_reset && !adev->gfx.in_suspend) {
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memset((void *)mqd, 0, sizeof(struct vi_mqd_allocation));
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((struct vi_mqd_allocation *)mqd)->dyamic_cu_mask = 0xFFFFFFFF;
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((struct vi_mqd_allocation *)mqd)->dyamic_rb_mask = 0xFFFFFFFF;
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mutex_lock(&adev->srbm_mutex);
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vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
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gfx_v8_0_mqd_init(ring);
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@ -4954,11 +4961,11 @@ static int gfx_v8_0_kcq_init_queue(struct amdgpu_ring *ring)
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mutex_unlock(&adev->srbm_mutex);
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if (adev->gfx.mec.mqd_backup[mqd_idx])
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memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
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memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct vi_mqd_allocation));
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} else if (adev->gfx.in_reset) { /* for GPU_RESET case */
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/* reset MQD to a clean status */
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if (adev->gfx.mec.mqd_backup[mqd_idx])
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memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
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memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct vi_mqd_allocation));
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/* reset ring buffer */
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ring->wptr = 0;
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amdgpu_ring_clear_ring(ring);
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@ -156,6 +156,274 @@ struct vi_sdma_mqd {
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};
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struct vi_mqd {
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uint32_t header;
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uint32_t compute_dispatch_initiator;
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uint32_t compute_dim_x;
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uint32_t compute_dim_y;
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uint32_t compute_dim_z;
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uint32_t compute_start_x;
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uint32_t compute_start_y;
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uint32_t compute_start_z;
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uint32_t compute_num_thread_x;
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uint32_t compute_num_thread_y;
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uint32_t compute_num_thread_z;
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uint32_t compute_pipelinestat_enable;
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uint32_t compute_perfcount_enable;
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uint32_t compute_pgm_lo;
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uint32_t compute_pgm_hi;
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uint32_t compute_tba_lo;
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uint32_t compute_tba_hi;
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uint32_t compute_tma_lo;
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uint32_t compute_tma_hi;
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uint32_t compute_pgm_rsrc1;
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uint32_t compute_pgm_rsrc2;
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uint32_t compute_vmid;
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uint32_t compute_resource_limits;
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uint32_t compute_static_thread_mgmt_se0;
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uint32_t compute_static_thread_mgmt_se1;
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uint32_t compute_tmpring_size;
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uint32_t compute_static_thread_mgmt_se2;
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uint32_t compute_static_thread_mgmt_se3;
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uint32_t compute_restart_x;
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uint32_t compute_restart_y;
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uint32_t compute_restart_z;
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uint32_t compute_thread_trace_enable;
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uint32_t compute_misc_reserved;
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uint32_t compute_dispatch_id;
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uint32_t compute_threadgroup_id;
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uint32_t compute_relaunch;
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uint32_t compute_wave_restore_addr_lo;
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uint32_t compute_wave_restore_addr_hi;
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uint32_t compute_wave_restore_control;
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uint32_t reserved9;
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uint32_t reserved10;
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uint32_t reserved11;
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uint32_t reserved12;
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uint32_t reserved13;
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uint32_t reserved14;
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uint32_t reserved15;
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uint32_t reserved16;
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uint32_t reserved17;
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uint32_t reserved18;
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uint32_t reserved19;
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uint32_t reserved20;
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uint32_t reserved21;
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uint32_t reserved22;
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uint32_t reserved23;
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uint32_t reserved24;
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uint32_t reserved25;
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uint32_t reserved26;
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uint32_t reserved27;
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uint32_t reserved28;
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uint32_t reserved29;
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uint32_t reserved30;
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uint32_t reserved31;
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uint32_t reserved32;
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uint32_t reserved33;
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uint32_t reserved34;
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uint32_t compute_user_data_0;
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uint32_t compute_user_data_1;
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uint32_t compute_user_data_2;
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uint32_t compute_user_data_3;
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uint32_t compute_user_data_4;
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uint32_t compute_user_data_5;
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uint32_t compute_user_data_6;
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uint32_t compute_user_data_7;
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uint32_t compute_user_data_8;
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uint32_t compute_user_data_9;
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uint32_t compute_user_data_10;
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uint32_t compute_user_data_11;
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uint32_t compute_user_data_12;
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uint32_t compute_user_data_13;
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uint32_t compute_user_data_14;
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uint32_t compute_user_data_15;
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uint32_t cp_compute_csinvoc_count_lo;
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uint32_t cp_compute_csinvoc_count_hi;
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uint32_t reserved35;
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uint32_t reserved36;
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uint32_t reserved37;
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uint32_t cp_mqd_query_time_lo;
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uint32_t cp_mqd_query_time_hi;
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uint32_t cp_mqd_connect_start_time_lo;
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uint32_t cp_mqd_connect_start_time_hi;
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uint32_t cp_mqd_connect_end_time_lo;
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uint32_t cp_mqd_connect_end_time_hi;
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uint32_t cp_mqd_connect_end_wf_count;
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uint32_t cp_mqd_connect_end_pq_rptr;
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uint32_t cp_mqd_connect_endvi_sdma_mqd_pq_wptr;
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uint32_t cp_mqd_connect_end_ib_rptr;
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uint32_t reserved38;
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uint32_t reserved39;
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uint32_t cp_mqd_save_start_time_lo;
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uint32_t cp_mqd_save_start_time_hi;
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uint32_t cp_mqd_save_end_time_lo;
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uint32_t cp_mqd_save_end_time_hi;
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uint32_t cp_mqd_restore_start_time_lo;
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uint32_t cp_mqd_restore_start_time_hi;
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uint32_t cp_mqd_restore_end_time_lo;
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uint32_t cp_mqd_restore_end_time_hi;
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uint32_t disable_queue;
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uint32_t reserved41;
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uint32_t gds_cs_ctxsw_cnt0;
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uint32_t gds_cs_ctxsw_cnt1;
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uint32_t gds_cs_ctxsw_cnt2;
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uint32_t gds_cs_ctxsw_cnt3;
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uint32_t reserved42;
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uint32_t reserved43;
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uint32_t cp_pq_exe_status_lo;
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uint32_t cp_pq_exe_status_hi;
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uint32_t cp_packet_id_lo;
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uint32_t cp_packet_id_hi;
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uint32_t cp_packet_exe_status_lo;
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uint32_t cp_packet_exe_status_hi;
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uint32_t gds_save_base_addr_lo;
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uint32_t gds_save_base_addr_hi;
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uint32_t gds_save_mask_lo;
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uint32_t gds_save_mask_hi;
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uint32_t ctx_save_base_addr_lo;
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uint32_t ctx_save_base_addr_hi;
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uint32_t dynamic_cu_mask_addr_lo;
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uint32_t dynamic_cu_mask_addr_hi;
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uint32_t cp_mqd_base_addr_lo;
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uint32_t cp_mqd_base_addr_hi;
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uint32_t cp_hqd_active;
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uint32_t cp_hqd_vmid;
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uint32_t cp_hqd_persistent_state;
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uint32_t cp_hqd_pipe_priority;
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uint32_t cp_hqd_queue_priority;
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uint32_t cp_hqd_quantum;
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uint32_t cp_hqd_pq_base_lo;
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uint32_t cp_hqd_pq_base_hi;
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uint32_t cp_hqd_pq_rptr;
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uint32_t cp_hqd_pq_rptr_report_addr_lo;
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uint32_t cp_hqd_pq_rptr_report_addr_hi;
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uint32_t cp_hqd_pq_wptr_poll_addr_lo;
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uint32_t cp_hqd_pq_wptr_poll_addr_hi;
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uint32_t cp_hqd_pq_doorbell_control;
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uint32_t cp_hqd_pq_wptr;
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uint32_t cp_hqd_pq_control;
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uint32_t cp_hqd_ib_base_addr_lo;
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uint32_t cp_hqd_ib_base_addr_hi;
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uint32_t cp_hqd_ib_rptr;
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uint32_t cp_hqd_ib_control;
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uint32_t cp_hqd_iq_timer;
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uint32_t cp_hqd_iq_rptr;
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uint32_t cp_hqd_dequeue_request;
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uint32_t cp_hqd_dma_offload;
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uint32_t cp_hqd_sema_cmd;
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uint32_t cp_hqd_msg_type;
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uint32_t cp_hqd_atomic0_preop_lo;
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uint32_t cp_hqd_atomic0_preop_hi;
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uint32_t cp_hqd_atomic1_preop_lo;
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uint32_t cp_hqd_atomic1_preop_hi;
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uint32_t cp_hqd_hq_status0;
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uint32_t cp_hqd_hq_control0;
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uint32_t cp_mqd_control;
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uint32_t cp_hqd_hq_status1;
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uint32_t cp_hqd_hq_control1;
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uint32_t cp_hqd_eop_base_addr_lo;
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uint32_t cp_hqd_eop_base_addr_hi;
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uint32_t cp_hqd_eop_control;
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uint32_t cp_hqd_eop_rptr;
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uint32_t cp_hqd_eop_wptr;
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uint32_t cp_hqd_eop_done_events;
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uint32_t cp_hqd_ctx_save_base_addr_lo;
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uint32_t cp_hqd_ctx_save_base_addr_hi;
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uint32_t cp_hqd_ctx_save_control;
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uint32_t cp_hqd_cntl_stack_offset;
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uint32_t cp_hqd_cntl_stack_size;
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uint32_t cp_hqd_wg_state_offset;
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uint32_t cp_hqd_ctx_save_size;
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uint32_t cp_hqd_gds_resource_state;
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uint32_t cp_hqd_error;
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uint32_t cp_hqd_eop_wptr_mem;
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uint32_t cp_hqd_eop_dones;
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uint32_t reserved46;
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uint32_t reserved47;
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uint32_t reserved48;
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uint32_t reserved49;
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uint32_t reserved50;
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uint32_t reserved51;
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uint32_t reserved52;
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uint32_t reserved53;
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uint32_t reserved54;
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uint32_t reserved55;
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uint32_t iqtimer_pkt_header;
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uint32_t iqtimer_pkt_dw0;
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uint32_t iqtimer_pkt_dw1;
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uint32_t iqtimer_pkt_dw2;
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uint32_t iqtimer_pkt_dw3;
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uint32_t iqtimer_pkt_dw4;
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uint32_t iqtimer_pkt_dw5;
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uint32_t iqtimer_pkt_dw6;
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uint32_t iqtimer_pkt_dw7;
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uint32_t iqtimer_pkt_dw8;
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uint32_t iqtimer_pkt_dw9;
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uint32_t iqtimer_pkt_dw10;
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uint32_t iqtimer_pkt_dw11;
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uint32_t iqtimer_pkt_dw12;
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uint32_t iqtimer_pkt_dw13;
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uint32_t iqtimer_pkt_dw14;
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uint32_t iqtimer_pkt_dw15;
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uint32_t iqtimer_pkt_dw16;
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uint32_t iqtimer_pkt_dw17;
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uint32_t iqtimer_pkt_dw18;
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uint32_t iqtimer_pkt_dw19;
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uint32_t iqtimer_pkt_dw20;
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uint32_t iqtimer_pkt_dw21;
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uint32_t iqtimer_pkt_dw22;
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uint32_t iqtimer_pkt_dw23;
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uint32_t iqtimer_pkt_dw24;
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uint32_t iqtimer_pkt_dw25;
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uint32_t iqtimer_pkt_dw26;
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uint32_t iqtimer_pkt_dw27;
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uint32_t iqtimer_pkt_dw28;
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uint32_t iqtimer_pkt_dw29;
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uint32_t iqtimer_pkt_dw30;
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uint32_t iqtimer_pkt_dw31;
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uint32_t reserved56;
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uint32_t reserved57;
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uint32_t reserved58;
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uint32_t set_resources_header;
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uint32_t set_resources_dw1;
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uint32_t set_resources_dw2;
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uint32_t set_resources_dw3;
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uint32_t set_resources_dw4;
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uint32_t set_resources_dw5;
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uint32_t set_resources_dw6;
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uint32_t set_resources_dw7;
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uint32_t reserved59;
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uint32_t reserved60;
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uint32_t reserved61;
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uint32_t reserved62;
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uint32_t reserved63;
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uint32_t reserved64;
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uint32_t reserved65;
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uint32_t reserved66;
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uint32_t reserved67;
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uint32_t reserved68;
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uint32_t reserved69;
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uint32_t reserved70;
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uint32_t reserved71;
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uint32_t reserved72;
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uint32_t reserved73;
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uint32_t reserved74;
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uint32_t reserved75;
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uint32_t reserved76;
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uint32_t reserved77;
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uint32_t reserved78;
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uint32_t reserved_t[256];
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};
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struct vi_mqd_allocation {
|
||||
struct vi_mqd mqd;
|
||||
uint32_t wptr_poll_mem;
|
||||
uint32_t rptr_report_mem;
|
||||
uint32_t dyamic_cu_mask;
|
||||
uint32_t dyamic_rb_mask;
|
||||
};
|
||||
|
||||
struct cz_mqd {
|
||||
uint32_t header;
|
||||
uint32_t compute_dispatch_initiator;
|
||||
uint32_t compute_dim_x;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user