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Merge branch 'for-rmk/perf' into for-rmk/virt/kvm/core

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This commit is contained in:
Will Deacon 2013-01-23 17:17:52 +00:00
commit 6abc749f63
6 changed files with 75 additions and 49 deletions
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33
arch/arm/include/asm/cputype.h
View File

@ -64,6 +64,24 @@ extern unsigned int processor_id;
#define read_cpuid_ext(reg) 0 #define read_cpuid_ext(reg) 0
#endif #endif
#define ARM_CPU_IMP_ARM 0x41
#define ARM_CPU_IMP_INTEL 0x69
#define ARM_CPU_PART_ARM1136 0xB360
#define ARM_CPU_PART_ARM1156 0xB560
#define ARM_CPU_PART_ARM1176 0xB760
#define ARM_CPU_PART_ARM11MPCORE 0xB020
#define ARM_CPU_PART_CORTEX_A8 0xC080
#define ARM_CPU_PART_CORTEX_A9 0xC090
#define ARM_CPU_PART_CORTEX_A5 0xC050
#define ARM_CPU_PART_CORTEX_A15 0xC0F0
#define ARM_CPU_PART_CORTEX_A7 0xC070
#define ARM_CPU_XSCALE_ARCH_MASK 0xe000
#define ARM_CPU_XSCALE_ARCH_V1 0x2000
#define ARM_CPU_XSCALE_ARCH_V2 0x4000
#define ARM_CPU_XSCALE_ARCH_V3 0x6000
/* /*
* The CPU ID never changes at run time, so we might as well tell the * The CPU ID never changes at run time, so we might as well tell the
* compiler that it's constant. Use this function to read the CPU ID * compiler that it's constant. Use this function to read the CPU ID
@ -74,6 +92,21 @@ static inline unsigned int __attribute_const__ read_cpuid_id(void)
return read_cpuid(CPUID_ID); return read_cpuid(CPUID_ID);
} }
static inline unsigned int __attribute_const__ read_cpuid_implementor(void)
{
return (read_cpuid_id() & 0xFF000000) >> 24;
}
static inline unsigned int __attribute_const__ read_cpuid_part_number(void)
{
return read_cpuid_id() & 0xFFF0;
}
static inline unsigned int __attribute_const__ xscale_cpu_arch_version(void)
{
return read_cpuid_part_number() & ARM_CPU_XSCALE_ARCH_MASK;
}
static inline unsigned int __attribute_const__ read_cpuid_cachetype(void) static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)
{ {
return read_cpuid(CPUID_CACHETYPE); return read_cpuid(CPUID_CACHETYPE);

16
arch/arm/kernel/perf_event.c
View File

@ -149,12 +149,6 @@ again:
static void static void
armpmu_read(struct perf_event *event) armpmu_read(struct perf_event *event)
{ {
struct hw_perf_event *hwc = &event->hw;
/* Don't read disabled counters! */
if (hwc->idx < 0)
return;
armpmu_event_update(event); armpmu_event_update(event);
} }
@ -207,8 +201,6 @@ armpmu_del(struct perf_event *event, int flags)
struct hw_perf_event *hwc = &event->hw; struct hw_perf_event *hwc = &event->hw;
int idx = hwc->idx; int idx = hwc->idx;
WARN_ON(idx < 0);
armpmu_stop(event, PERF_EF_UPDATE); armpmu_stop(event, PERF_EF_UPDATE);
hw_events->events[idx] = NULL; hw_events->events[idx] = NULL;
clear_bit(idx, hw_events->used_mask); clear_bit(idx, hw_events->used_mask);
@ -358,7 +350,7 @@ __hw_perf_event_init(struct perf_event *event)
{ {
struct arm_pmu *armpmu = to_arm_pmu(event->pmu); struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
struct hw_perf_event *hwc = &event->hw; struct hw_perf_event *hwc = &event->hw;
int mapping, err; int mapping;
mapping = armpmu->map_event(event); mapping = armpmu->map_event(event);
@ -407,14 +399,12 @@ __hw_perf_event_init(struct perf_event *event)
local64_set(&hwc->period_left, hwc->sample_period); local64_set(&hwc->period_left, hwc->sample_period);
} }
err = 0;
if (event->group_leader != event) { if (event->group_leader != event) {
err = validate_group(event); if (validate_group(event) != 0);
if (err)
return -EINVAL; return -EINVAL;
} }
return err; return 0;
} }
static int armpmu_event_init(struct perf_event *event) static int armpmu_event_init(struct perf_event *event)

51
arch/arm/kernel/perf_event_cpu.c
View File

@ -147,7 +147,7 @@ static void cpu_pmu_init(struct arm_pmu *cpu_pmu)
cpu_pmu->free_irq = cpu_pmu_free_irq; cpu_pmu->free_irq = cpu_pmu_free_irq;
/* Ensure the PMU has sane values out of reset. */ /* Ensure the PMU has sane values out of reset. */
if (cpu_pmu && cpu_pmu->reset) if (cpu_pmu->reset)
on_each_cpu(cpu_pmu->reset, cpu_pmu, 1); on_each_cpu(cpu_pmu->reset, cpu_pmu, 1);
} }
@ -201,48 +201,46 @@ static struct platform_device_id cpu_pmu_plat_device_ids[] = {
static int probe_current_pmu(struct arm_pmu *pmu) static int probe_current_pmu(struct arm_pmu *pmu)
{ {
int cpu = get_cpu(); int cpu = get_cpu();
unsigned long cpuid = read_cpuid_id(); unsigned long implementor = read_cpuid_implementor();
unsigned long implementor = (cpuid & 0xFF000000) >> 24; unsigned long part_number = read_cpuid_part_number();
unsigned long part_number = (cpuid & 0xFFF0);
int ret = -ENODEV; int ret = -ENODEV;
pr_info("probing PMU on CPU %d\n", cpu); pr_info("probing PMU on CPU %d\n", cpu);
/* ARM Ltd CPUs. */ /* ARM Ltd CPUs. */
if (0x41 == implementor) { if (implementor == ARM_CPU_IMP_ARM) {
switch (part_number) { switch (part_number) {
case 0xB360: /* ARM1136 */ case ARM_CPU_PART_ARM1136:
case 0xB560: /* ARM1156 */ case ARM_CPU_PART_ARM1156:
case 0xB760: /* ARM1176 */ case ARM_CPU_PART_ARM1176:
ret = armv6pmu_init(pmu); ret = armv6pmu_init(pmu);
break; break;
case 0xB020: /* ARM11mpcore */ case ARM_CPU_PART_ARM11MPCORE:
ret = armv6mpcore_pmu_init(pmu); ret = armv6mpcore_pmu_init(pmu);
break; break;
case 0xC080: /* Cortex-A8 */ case ARM_CPU_PART_CORTEX_A8:
ret = armv7_a8_pmu_init(pmu); ret = armv7_a8_pmu_init(pmu);
break; break;
case 0xC090: /* Cortex-A9 */ case ARM_CPU_PART_CORTEX_A9:
ret = armv7_a9_pmu_init(pmu); ret = armv7_a9_pmu_init(pmu);
break; break;
case 0xC050: /* Cortex-A5 */ case ARM_CPU_PART_CORTEX_A5:
ret = armv7_a5_pmu_init(pmu); ret = armv7_a5_pmu_init(pmu);
break; break;
case 0xC0F0: /* Cortex-A15 */ case ARM_CPU_PART_CORTEX_A15:
ret = armv7_a15_pmu_init(pmu); ret = armv7_a15_pmu_init(pmu);
break; break;
case 0xC070: /* Cortex-A7 */ case ARM_CPU_PART_CORTEX_A7:
ret = armv7_a7_pmu_init(pmu); ret = armv7_a7_pmu_init(pmu);
break; break;
} }
/* Intel CPUs [xscale]. */ /* Intel CPUs [xscale]. */
} else if (0x69 == implementor) { } else if (implementor == ARM_CPU_IMP_INTEL) {
part_number = (cpuid >> 13) & 0x7; switch (xscale_cpu_arch_version()) {
switch (part_number) { case ARM_CPU_XSCALE_ARCH_V1:
case 1:
ret = xscale1pmu_init(pmu); ret = xscale1pmu_init(pmu);
break; break;
case 2: case ARM_CPU_XSCALE_ARCH_V2:
ret = xscale2pmu_init(pmu); ret = xscale2pmu_init(pmu);
break; break;
} }
@ -279,17 +277,22 @@ static int cpu_pmu_device_probe(struct platform_device *pdev)
} }
if (ret) { if (ret) {
pr_info("failed to register PMU devices!"); pr_info("failed to probe PMU!");
kfree(pmu); goto out_free;
return ret;
} }
cpu_pmu = pmu; cpu_pmu = pmu;
cpu_pmu->plat_device = pdev; cpu_pmu->plat_device = pdev;
cpu_pmu_init(cpu_pmu); cpu_pmu_init(cpu_pmu);
armpmu_register(cpu_pmu, PERF_TYPE_RAW); ret = armpmu_register(cpu_pmu, PERF_TYPE_RAW);
return 0; if (!ret)
return 0;
out_free:
pr_info("failed to register PMU devices!");
kfree(pmu);
return ret;
} }
static struct platform_driver cpu_pmu_driver = { static struct platform_driver cpu_pmu_driver = {

4
arch/arm/kernel/perf_event_v6.c
View File

@ -106,7 +106,7 @@ static const unsigned armv6_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
}, },
[C(OP_WRITE)] = { [C(OP_WRITE)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
[C(RESULT_MISS)] = ARMV6_PERFCTR_ICACHE_MISS, [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
}, },
[C(OP_PREFETCH)] = { [C(OP_PREFETCH)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
@ -259,7 +259,7 @@ static const unsigned armv6mpcore_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
}, },
[C(OP_WRITE)] = { [C(OP_WRITE)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
[C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_ICACHE_MISS, [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
}, },
[C(OP_PREFETCH)] = { [C(OP_PREFETCH)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,

18
arch/arm/kernel/perf_event_v7.c
View File

@ -157,8 +157,8 @@ static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
[C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
}, },
[C(OP_WRITE)] = { [C(OP_WRITE)] = {
[C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS, [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
[C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
}, },
[C(OP_PREFETCH)] = { [C(OP_PREFETCH)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
@ -282,7 +282,7 @@ static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
}, },
[C(OP_WRITE)] = { [C(OP_WRITE)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
[C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
}, },
[C(OP_PREFETCH)] = { [C(OP_PREFETCH)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
@ -399,8 +399,8 @@ static const unsigned armv7_a5_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
[C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
}, },
[C(OP_WRITE)] = { [C(OP_WRITE)] = {
[C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS, [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
[C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
}, },
/* /*
* The prefetch counters don't differentiate between the I * The prefetch counters don't differentiate between the I
@ -527,8 +527,8 @@ static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
[C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
}, },
[C(OP_WRITE)] = { [C(OP_WRITE)] = {
[C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS, [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
[C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
}, },
[C(OP_PREFETCH)] = { [C(OP_PREFETCH)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
@ -651,8 +651,8 @@ static const unsigned armv7_a7_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
[C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
}, },
[C(OP_WRITE)] = { [C(OP_WRITE)] = {
[C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS, [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
[C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
}, },
[C(OP_PREFETCH)] = { [C(OP_PREFETCH)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,

2
arch/arm/kernel/perf_event_xscale.c
View File

@ -83,7 +83,7 @@ static const unsigned xscale_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
}, },
[C(OP_WRITE)] = { [C(OP_WRITE)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
[C(RESULT_MISS)] = XSCALE_PERFCTR_ICACHE_MISS, [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
}, },
[C(OP_PREFETCH)] = { [C(OP_PREFETCH)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,