forked from Minki/linux
Merge branch 'irq-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip
* 'irq-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: avr32: Fix missing irq namespace conversion powerpc: qe_ic: Rename get_irq_desc_data and get_irq_desc_chip genirq: Remove the now obsolete config options and select statements arm: versatile : Fix typo introduced in irq namespace cleanup sound: Fixup the last user of the old irq functions genirq: Remove obsolete comment genirq: Remove now obsolete set_irq_wake() sh: Fix irq cleanup fallout x86: apb_timer: Fixup genirq fallout genirq: Fix misnamed label in handle_edge_eoi_irq Fix up crazy conflict in arch/powerpc/include/asm/qe_ic.h: - commiteead4d5c63
("powerpc: qe_ic: Rename get_irq_desc_data and get_irq_desc_chip") made the helper functions use irq_desc_get_handler_data() instead of the legacy (and no longer existing) get_irq_desc_data. - commitd4db35e8dc
("powerpc/qe_ic: Fix another breakage from the irq_data conversion") used irq_desc_get_chip_data() instead. According to Thomas, the former is the correct direct conversion, but it does look like both should work (arch/powerpc/sysdev/qe_lib/qe_ic.c seems to initialize both to the same thing), and the chip data in some ways is the more logical. Somebody should really decide on one of the other. This merge picks irq_desc_get_handler_data() as the straightforward pure conversion to new names, as per Thomas.
This commit is contained in:
commit
6aba74f279
@ -12,7 +12,6 @@ config ALPHA
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select GENERIC_IRQ_PROBE
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select AUTO_IRQ_AFFINITY if SMP
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select GENERIC_IRQ_SHOW
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select GENERIC_HARDIRQS_NO_DEPRECATED
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help
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The Alpha is a 64-bit general-purpose processor designed and
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marketed by the Digital Equipment Corporation of blessed memory,
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@ -314,7 +314,7 @@ static struct mmci_platform_data mmc0_plat_data = {
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.gpio_cd = -1,
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};
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static struct resource chalcd_resources[] = {
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static struct resource char_lcd_resources[] = {
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{
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.start = VERSATILE_CHAR_LCD_BASE,
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.end = (VERSATILE_CHAR_LCD_BASE + SZ_4K - 1),
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@ -10,7 +10,6 @@ config AVR32
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select GENERIC_IRQ_PROBE
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select HARDIRQS_SW_RESEND
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select GENERIC_IRQ_SHOW
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select GENERIC_HARDIRQS_NO_DEPRECATED
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help
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AVR32 is a high-performance 32-bit RISC microprocessor core,
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designed for cost-sensitive embedded applications, with particular
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@ -282,7 +282,7 @@ static struct irq_chip gpio_irqchip = {
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static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
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{
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struct pio_device *pio = get_irq_desc_chip_data(desc);
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struct pio_device *pio = irq_desc_get_chip_data(desc);
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unsigned gpio_irq;
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gpio_irq = (unsigned) irq_get_handler_data(irq);
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@ -34,7 +34,6 @@ config BLACKFIN
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select GENERIC_ATOMIC64
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select GENERIC_IRQ_PROBE
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select IRQ_PER_CPU if SMP
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select GENERIC_HARDIRQS_NO_DEPRECATED
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config GENERIC_CSUM
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def_bool y
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@ -55,7 +55,6 @@ config CRIS
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default y
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select HAVE_IDE
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select HAVE_GENERIC_HARDIRQS
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select GENERIC_HARDIRQS_NO_DEPRECATED
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select GENERIC_IRQ_SHOW
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config HZ
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@ -7,7 +7,6 @@ config FRV
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select HAVE_PERF_EVENTS
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select HAVE_GENERIC_HARDIRQS
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select GENERIC_IRQ_SHOW
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select GENERIC_HARDIRQS_NO_DEPRECATED
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config ZONE_DMA
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bool
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@ -3,7 +3,6 @@ config H8300
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default y
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select HAVE_IDE
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select HAVE_GENERIC_HARDIRQS
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select GENERIC_HARDIRQS_NO_DEPRECATED
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select GENERIC_IRQ_SHOW
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config SYMBOL_PREFIX
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@ -8,7 +8,6 @@ config M32R
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select HAVE_KERNEL_BZIP2
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select HAVE_KERNEL_LZMA
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select HAVE_GENERIC_HARDIRQS
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select GENERIC_HARDIRQS_NO_DEPRECATED
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select GENERIC_IRQ_PROBE
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select GENERIC_IRQ_SHOW
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@ -5,7 +5,6 @@ config M68K
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select HAVE_AOUT if MMU
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select GENERIC_ATOMIC64 if MMU
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select HAVE_GENERIC_HARDIRQS if !MMU
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select GENERIC_HARDIRQS_NO_DEPRECATED if !MMU
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config RWSEM_GENERIC_SPINLOCK
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bool
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@ -17,7 +17,6 @@ config MICROBLAZE
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select OF_EARLY_FLATTREE
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select HAVE_GENERIC_HARDIRQS
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select GENERIC_IRQ_PROBE
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select GENERIC_HARDIRQS_NO_DEPRECATED
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select GENERIC_IRQ_SHOW
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config SWAP
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@ -2,7 +2,6 @@ config MN10300
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def_bool y
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select HAVE_OPROFILE
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select HAVE_GENERIC_HARDIRQS
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select GENERIC_HARDIRQS_NO_DEPRECATED
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select GENERIC_IRQ_SHOW
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select HAVE_ARCH_TRACEHOOK
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select HAVE_ARCH_KGDB
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@ -15,7 +15,6 @@ config PARISC
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select HAVE_GENERIC_HARDIRQS
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select GENERIC_IRQ_PROBE
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select IRQ_PER_CPU
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select GENERIC_HARDIRQS_NO_DEPRECATED
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help
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The PA-RISC microprocessor is designed by Hewlett-Packard and used
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@ -138,7 +138,6 @@ config PPC
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select HAVE_GENERIC_HARDIRQS
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select HAVE_SPARSE_IRQ
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select IRQ_PER_CPU
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select GENERIC_HARDIRQS_NO_DEPRECATED
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select GENERIC_IRQ_SHOW
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select GENERIC_IRQ_SHOW_LEVEL
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@ -81,7 +81,7 @@ int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high);
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static inline void qe_ic_cascade_low_ipic(unsigned int irq,
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struct irq_desc *desc)
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{
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struct qe_ic *qe_ic = irq_desc_get_chip_data(desc);
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struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
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unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
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if (cascade_irq != NO_IRQ)
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@ -91,7 +91,7 @@ static inline void qe_ic_cascade_low_ipic(unsigned int irq,
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static inline void qe_ic_cascade_high_ipic(unsigned int irq,
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struct irq_desc *desc)
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{
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struct qe_ic *qe_ic = irq_desc_get_chip_data(desc);
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struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
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unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
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if (cascade_irq != NO_IRQ)
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@ -101,7 +101,7 @@ static inline void qe_ic_cascade_high_ipic(unsigned int irq,
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static inline void qe_ic_cascade_low_mpic(unsigned int irq,
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struct irq_desc *desc)
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{
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struct qe_ic *qe_ic = irq_desc_get_chip_data(desc);
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struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
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unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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@ -114,7 +114,7 @@ static inline void qe_ic_cascade_low_mpic(unsigned int irq,
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static inline void qe_ic_cascade_high_mpic(unsigned int irq,
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struct irq_desc *desc)
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{
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struct qe_ic *qe_ic = irq_desc_get_chip_data(desc);
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struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
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unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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@ -127,7 +127,7 @@ static inline void qe_ic_cascade_high_mpic(unsigned int irq,
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static inline void qe_ic_cascade_muxed_mpic(unsigned int irq,
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struct irq_desc *desc)
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{
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struct qe_ic *qe_ic = irq_desc_get_chip_data(desc);
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struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
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unsigned int cascade_irq;
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struct irq_chip *chip = irq_desc_get_chip(desc);
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@ -3,7 +3,6 @@ menu "Machine selection"
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config SCORE
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def_bool y
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select HAVE_GENERIC_HARDIRQS
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select GENERIC_HARDIRQS_NO_DEPRECATED
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select GENERIC_IRQ_SHOW
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choice
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@ -23,7 +23,6 @@ config SUPERH
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select HAVE_SPARSE_IRQ
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select RTC_LIB
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select GENERIC_ATOMIC64
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select GENERIC_HARDIRQS_NO_DEPRECATED
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select GENERIC_IRQ_SHOW
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help
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The SuperH is a RISC processor targeted for use in embedded systems
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@ -51,7 +51,6 @@ config SPARC64
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select HAVE_PERF_EVENTS
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select PERF_USE_VMALLOC
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select HAVE_GENERIC_HARDIRQS
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select GENERIC_HARDIRQS_NO_DEPRECATED
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select GENERIC_IRQ_SHOW
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select IRQ_PREFLOW_FASTEOI
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@ -11,7 +11,6 @@ config TILE
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select HAVE_GENERIC_HARDIRQS
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select GENERIC_IRQ_PROBE
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select GENERIC_PENDING_IRQ if SMP
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select GENERIC_HARDIRQS_NO_DEPRECATED
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select GENERIC_IRQ_SHOW
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# FIXME: investigate whether we need/want these options.
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@ -7,7 +7,6 @@ config UML
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bool
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default y
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select HAVE_GENERIC_HARDIRQS
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select GENERIC_HARDIRQS_NO_DEPRECATED
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select GENERIC_IRQ_SHOW
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config MMU
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@ -10,7 +10,6 @@ config UNICORE32
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select HAVE_KERNEL_LZMA
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select GENERIC_FIND_FIRST_BIT
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select GENERIC_IRQ_PROBE
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select GENERIC_HARDIRQS_NO_DEPRECATED
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select GENERIC_IRQ_SHOW
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select ARCH_WANT_FRAME_POINTERS
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help
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@ -316,7 +316,7 @@ static void apbt_setup_irq(struct apbt_dev *adev)
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irq_modify_status(adev->irq, 0, IRQ_MOVE_PCNTXT);
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irq_set_affinity(adev->irq, cpumask_of(adev->cpu));
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/* APB timer irqs are set up as mp_irqs, timer is edge type */
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__set_irq_handler(adev->irq, handle_edge_irq, 0, "edge");
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__irq_set_handler(adev->irq, handle_edge_irq, 0, "edge");
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if (system_state == SYSTEM_BOOTING) {
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if (request_irq(adev->irq, apbt_interrupt_handler,
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@ -9,7 +9,6 @@ config XTENSA
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select HAVE_IDE
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select HAVE_GENERIC_HARDIRQS
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select GENERIC_IRQ_SHOW
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select GENERIC_HARDIRQS_NO_DEPRECATED
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help
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Xtensa processors are 32-bit RISC machines designed by Tensilica
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primarily for embedded systems. These processors are both
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@ -86,7 +86,7 @@ enum { MODE_ENABLE_REG = 0, /* Bit(s) set -> interrupt enabled */
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static inline struct intc_desc_int *get_intc_desc(unsigned int irq)
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{
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struct irq_chip *chip = get_irq_chip(irq);
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struct irq_chip *chip = irq_get_chip(irq);
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return container_of(chip, struct intc_desc_int, chip);
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}
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@ -103,7 +103,7 @@ static inline void activate_irq(int irq)
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set_irq_flags(irq, IRQF_VALID);
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#else
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/* same effect on other architectures */
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set_irq_noprobe(irq);
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irq_set_noprobe(irq);
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#endif
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}
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/* IRQ wakeup (PM) control: */
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extern int irq_set_irq_wake(unsigned int irq, unsigned int on);
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#ifndef CONFIG_GENERIC_HARDIRQS_NO_COMPAT
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/* Please do not use: Use the replacement functions instead */
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static inline int set_irq_wake(unsigned int irq, unsigned int on)
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{
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return irq_set_irq_wake(irq, on);
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}
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#endif
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static inline int enable_irq_wake(unsigned int irq)
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{
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return irq_set_irq_wake(irq, 1);
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* IRQ_NO_BALANCING - Interrupt cannot be balanced (affinity set)
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* IRQ_MOVE_PCNTXT - Interrupt can be migrated from process context
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* IRQ_NESTED_TRHEAD - Interrupt nests into another thread
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*
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* Deprecated bits. They are kept updated as long as
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* CONFIG_GENERIC_HARDIRQS_NO_COMPAT is not set. Will go away soon. These bits
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* are internal state of the core code and if you really need to acces
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* them then talk to the genirq maintainer instead of hacking
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* something weird.
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*
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*/
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enum {
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IRQ_TYPE_NONE = 0x00000000,
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@ -10,9 +10,6 @@ menu "IRQ subsystem"
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config GENERIC_HARDIRQS
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def_bool y
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config GENERIC_HARDIRQS_NO_COMPAT
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bool
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# Options selectable by the architecture code
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# Make sparse irq Kconfig switch below available
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@ -331,7 +331,7 @@ int snd_soc_jack_add_gpios(struct snd_soc_jack *jack, int count,
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goto err;
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if (gpios[i].wake) {
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ret = set_irq_wake(gpio_to_irq(gpios[i].gpio), 1);
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ret = irq_set_irq_wake(gpio_to_irq(gpios[i].gpio), 1);
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if (ret != 0)
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printk(KERN_ERR
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"Failed to mark GPIO %d as wake source: %d\n",
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