ath9k: content DMA start / stop through the PCU lock
This helps align resets / RX enable & disable / TX stop / start. Locking around the PCU is important to ensure the hardware doesn't get stale data when working with DMA'able data. This is part of a series of patches which fix stopping TX DMA completley when requested on the driver. For more details about this issue refer to this thread: http://marc.info/?l=linux-wireless&m=128629803703756&w=2 Tested-by: Ben Greear <greearb@candelatech.com> Cc: Kyungwan Nam <kyungwan.nam@atheros.com> Cc: stable@kernel.org Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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4bdd1e978e
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@ -230,6 +230,8 @@ int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
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ath9k_ps_wakeup(sc);
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spin_lock_bh(&sc->sc_pcu_lock);
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/*
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* This is only performed if the channel settings have
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* actually changed.
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@ -242,8 +244,6 @@ int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
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ath9k_hw_disable_interrupts(ah);
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ath_drain_all_txq(sc, false);
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spin_lock_bh(&sc->sc_pcu_lock);
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stopped = ath_stoprecv(sc);
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/* XXX: do not flush receive queue here. We don't want
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@ -268,7 +268,6 @@ int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
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"Unable to reset channel (%u MHz), "
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"reset status %d\n",
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channel->center_freq, r);
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spin_unlock_bh(&sc->sc_pcu_lock);
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goto ps_restore;
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}
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@ -276,12 +275,9 @@ int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
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ath_print(common, ATH_DBG_FATAL,
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"Unable to restart recv logic\n");
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r = -EIO;
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spin_unlock_bh(&sc->sc_pcu_lock);
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goto ps_restore;
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}
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spin_unlock_bh(&sc->sc_pcu_lock);
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ath_update_txpow(sc);
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ath9k_hw_set_interrupts(ah, ah->imask);
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@ -292,6 +288,8 @@ int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
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}
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ps_restore:
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spin_unlock_bh(&sc->sc_pcu_lock);
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ath9k_ps_restore(sc);
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return r;
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}
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@ -605,6 +603,8 @@ void ath9k_tasklet(unsigned long data)
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return;
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}
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spin_lock_bh(&sc->sc_pcu_lock);
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if (!ath9k_hw_check_alive(ah))
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ieee80211_queue_work(sc->hw, &sc->hw_check_work);
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@ -615,15 +615,12 @@ void ath9k_tasklet(unsigned long data)
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rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
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if (status & rxmask) {
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spin_lock_bh(&sc->sc_pcu_lock);
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/* Check for high priority Rx first */
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if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
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(status & ATH9K_INT_RXHP))
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ath_rx_tasklet(sc, 0, true);
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ath_rx_tasklet(sc, 0, false);
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spin_unlock_bh(&sc->sc_pcu_lock);
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}
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if (status & ATH9K_INT_TX) {
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@ -649,6 +646,8 @@ void ath9k_tasklet(unsigned long data)
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/* re-enable hardware interrupt */
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ath9k_hw_enable_interrupts(ah);
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spin_unlock_bh(&sc->sc_pcu_lock);
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ath9k_ps_restore(sc);
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}
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@ -876,12 +875,13 @@ void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw)
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int r;
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ath9k_ps_wakeup(sc);
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spin_lock_bh(&sc->sc_pcu_lock);
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ath9k_hw_configpcipowersave(ah, 0, 0);
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if (!ah->curchan)
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ah->curchan = ath_get_curchannel(sc, sc->hw);
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spin_lock_bh(&sc->sc_pcu_lock);
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r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
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if (r) {
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ath_print(common, ATH_DBG_FATAL,
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@ -897,8 +897,6 @@ void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw)
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spin_unlock_bh(&sc->sc_pcu_lock);
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return;
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}
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spin_unlock_bh(&sc->sc_pcu_lock);
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if (sc->sc_flags & SC_OP_BEACONS)
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ath_beacon_config(sc, NULL); /* restart beacons */
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@ -911,6 +909,8 @@ void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw)
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ath9k_hw_set_gpio(ah, ah->led_pin, 0);
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ieee80211_wake_queues(hw);
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spin_unlock_bh(&sc->sc_pcu_lock);
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ath9k_ps_restore(sc);
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}
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@ -921,6 +921,8 @@ void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw)
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int r;
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ath9k_ps_wakeup(sc);
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spin_lock_bh(&sc->sc_pcu_lock);
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ieee80211_stop_queues(hw);
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/*
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@ -937,8 +939,6 @@ void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw)
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ath_drain_all_txq(sc, false); /* clear pending tx frames */
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spin_lock_bh(&sc->sc_pcu_lock);
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ath_stoprecv(sc); /* turn off frame recv */
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ath_flushrecv(sc); /* flush recv queue */
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@ -955,10 +955,11 @@ void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw)
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ath9k_hw_phy_disable(ah);
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spin_unlock_bh(&sc->sc_pcu_lock);
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ath9k_hw_configpcipowersave(ah, 1, 1);
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spin_unlock_bh(&sc->sc_pcu_lock);
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ath9k_ps_restore(sc);
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ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
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}
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@ -972,13 +973,13 @@ int ath_reset(struct ath_softc *sc, bool retry_tx)
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/* Stop ANI */
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del_timer_sync(&common->ani.timer);
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spin_lock_bh(&sc->sc_pcu_lock);
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ieee80211_stop_queues(hw);
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ath9k_hw_disable_interrupts(ah);
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ath_drain_all_txq(sc, retry_tx);
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spin_lock_bh(&sc->sc_pcu_lock);
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ath_stoprecv(sc);
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ath_flushrecv(sc);
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@ -991,8 +992,6 @@ int ath_reset(struct ath_softc *sc, bool retry_tx)
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ath_print(common, ATH_DBG_FATAL,
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"Unable to start recv logic\n");
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spin_unlock_bh(&sc->sc_pcu_lock);
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/*
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* We may be doing a reset in response to a request
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* that changes the channel so update any state that
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@ -1017,6 +1016,7 @@ int ath_reset(struct ath_softc *sc, bool retry_tx)
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}
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ieee80211_wake_queues(hw);
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spin_unlock_bh(&sc->sc_pcu_lock);
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/* Start ANI */
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ath_start_ani(common);
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@ -1381,25 +1381,25 @@ static void ath9k_stop(struct ieee80211_hw *hw)
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ath9k_btcoex_timer_pause(sc);
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}
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spin_lock_bh(&sc->sc_pcu_lock);
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/* make sure h/w will not generate any interrupt
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* before setting the invalid flag. */
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ath9k_hw_disable_interrupts(ah);
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if (!(sc->sc_flags & SC_OP_INVALID)) {
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ath_drain_all_txq(sc, false);
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spin_lock_bh(&sc->sc_pcu_lock);
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ath_stoprecv(sc);
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ath9k_hw_phy_disable(ah);
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spin_unlock_bh(&sc->sc_pcu_lock);
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} else {
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spin_lock_bh(&sc->sc_pcu_lock);
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} else
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sc->rx.rxlink = NULL;
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spin_unlock_bh(&sc->sc_pcu_lock);
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}
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/* disable HAL and put h/w to sleep */
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ath9k_hw_disable(ah);
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ath9k_hw_configpcipowersave(ah, 1, 1);
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spin_unlock_bh(&sc->sc_pcu_lock);
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ath9k_ps_restore(sc);
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/* Finally, put the chip in FULL SLEEP mode */
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@ -1148,13 +1148,11 @@ void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
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ath_print(common, ATH_DBG_FATAL,
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"Failed to stop TX DMA. Resetting hardware!\n");
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spin_lock_bh(&sc->sc_pcu_lock);
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r = ath9k_hw_reset(ah, sc->sc_ah->curchan, ah->caldata, false);
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if (r)
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ath_print(common, ATH_DBG_FATAL,
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"Unable to reset hardware; reset status %d\n",
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r);
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spin_unlock_bh(&sc->sc_pcu_lock);
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}
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for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
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