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dt: amd-seattle: add a description of the CPUs and caches

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Add a DT description of the CPU and cache hierarchy as found on
the AMD Seattle SOC. Given the tight coupling of the PMU with
the CPUs, move the PMU node into the cpu .dtsi file as well, and
add the missing affinity description.

Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Ard Biesheuvel 2019-12-03 15:23:06 +00:00 committed by Arnd Bergmann
parent e0db1597a7
commit 6a2f0b2d3b
No known key found for this signature in database
GPG Key ID: 9A6C79EFE60018D9
4 changed files with 226 additions and 12 deletions

1
arch/arm64/boot/dts/amd/amd-overdrive-rev-b0.dts
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@ -9,6 +9,7 @@
/dts-v1/;
/include/ "amd-seattle-soc.dtsi"
/include/ "amd-seattle-cpus.dtsi"
/ {
model = "AMD Seattle (Rev.B0) Development Board (Overdrive)";

1
arch/arm64/boot/dts/amd/amd-overdrive-rev-b1.dts
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@ -9,6 +9,7 @@
/dts-v1/;
/include/ "amd-seattle-soc.dtsi"
/include/ "amd-seattle-cpus.dtsi"
/ {
model = "AMD Seattle (Rev.B1) Development Board (Overdrive)";

224
arch/arm64/boot/dts/amd/amd-seattle-cpus.dtsi Normal file
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@ -0,0 +1,224 @@
// SPDX-License-Identifier: GPL-2.0
/ {
cpus {
#address-cells = <0x1>;
#size-cells = <0x0>;
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
};
core1 {
cpu = <&CPU1>;
};
};
cluster1 {
core0 {
cpu = <&CPU2>;
};
core1 {
cpu = <&CPU3>;
};
};
cluster2 {
core0 {
cpu = <&CPU4>;
};
core1 {
cpu = <&CPU5>;
};
};
cluster3 {
core0 {
cpu = <&CPU6>;
};
core1 {
cpu = <&CPU7>;
};
};
};
CPU0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0>;
enable-method = "psci";
i-cache-size = <0xC000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
l2-cache = <&L2_0>;
};
CPU1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x1>;
enable-method = "psci";
i-cache-size = <0xC000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
l2-cache = <&L2_0>;
};
CPU2: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x100>;
enable-method = "psci";
i-cache-size = <0xC000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
l2-cache = <&L2_1>;
};
CPU3: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x101>;
enable-method = "psci";
i-cache-size = <0xC000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
l2-cache = <&L2_1>;
};
CPU4: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x200>;
enable-method = "psci";
i-cache-size = <0xC000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
l2-cache = <&L2_2>;
};
CPU5: cpu@201 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x201>;
enable-method = "psci";
i-cache-size = <0xC000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
l2-cache = <&L2_2>;
};
CPU6: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x300>;
enable-method = "psci";
i-cache-size = <0xC000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
l2-cache = <&L2_3>;
};
CPU7: cpu@301 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x301>;
enable-method = "psci";
i-cache-size = <0xC000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
l2-cache = <&L2_3>;
};
};
L2_0: l2-cache0 {
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
cache-unified;
next-level-cache = <&L3>;
};
L2_1: l2-cache1 {
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
cache-unified;
next-level-cache = <&L3>;
};
L2_2: l2-cache2 {
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
cache-unified;
next-level-cache = <&L3>;
};
L2_3: l2-cache3 {
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
cache-unified;
next-level-cache = <&L3>;
};
L3: l3-cache {
cache-level = <3>;
cache-size = <0x800000>;
cache-line-size = <64>;
cache-sets = <8192>;
cache-unified;
};
pmu {
compatible = "arm,cortex-a57-pmu";
interrupts = <0x0 0x7 0x4>,
<0x0 0x8 0x4>,
<0x0 0x9 0x4>,
<0x0 0xa 0x4>,
<0x0 0xb 0x4>,
<0x0 0xc 0x4>,
<0x0 0xd 0x4>,
<0x0 0xe 0x4>;
interrupt-affinity = <&CPU0>,
<&CPU1>,
<&CPU2>,
<&CPU3>,
<&CPU4>,
<&CPU5>,
<&CPU6>,
<&CPU7>;
};
};

12
arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi
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@ -38,18 +38,6 @@
<1 10 0xff04>;
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <0 7 4>,
<0 8 4>,
<0 9 4>,
<0 10 4>,
<0 11 4>,
<0 12 4>,
<0 13 4>,
<0 14 4>;
};
smb0: smb {
compatible = "simple-bus";
#address-cells = <2>;