forked from Minki/linux
ARM: l2c: add L2C-210 specific handlers
Add L2C-210 specific cache operation handlers. These are tailored to the requirements of the L2C-210 cache controller, which doesn't require any workarounds. We avoid using the way operations during normal operation, which means we can avoid locking: the only time we use the way operations are during initialisation, and when disabling the cache. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -388,6 +388,108 @@ static const struct l2c_init_data l2x0_init_fns __initconst = {
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},
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};
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/*
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* L2C-210 specific code.
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*
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* The L2C-2x0 PA, set/way and sync operations are atomic, but we must
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* ensure that no background operation is running. The way operations
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* are all background tasks.
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*
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* While a background operation is in progress, any new operation is
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* ignored (unspecified whether this causes an error.) Thankfully, not
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* used on SMP.
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*
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* Never has a different sync register other than L2X0_CACHE_SYNC, but
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* we use sync_reg_offset here so we can share some of this with L2C-310.
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*/
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static void __l2c210_cache_sync(void __iomem *base)
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{
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writel_relaxed(0, base + sync_reg_offset);
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}
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static void __l2c210_op_pa_range(void __iomem *reg, unsigned long start,
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unsigned long end)
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{
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while (start < end) {
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writel_relaxed(start, reg);
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start += CACHE_LINE_SIZE;
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}
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}
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static void l2c210_inv_range(unsigned long start, unsigned long end)
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{
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void __iomem *base = l2x0_base;
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if (start & (CACHE_LINE_SIZE - 1)) {
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start &= ~(CACHE_LINE_SIZE - 1);
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writel_relaxed(start, base + L2X0_CLEAN_INV_LINE_PA);
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start += CACHE_LINE_SIZE;
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}
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if (end & (CACHE_LINE_SIZE - 1)) {
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end &= ~(CACHE_LINE_SIZE - 1);
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writel_relaxed(end, base + L2X0_CLEAN_INV_LINE_PA);
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}
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__l2c210_op_pa_range(base + L2X0_INV_LINE_PA, start, end);
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__l2c210_cache_sync(base);
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}
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static void l2c210_clean_range(unsigned long start, unsigned long end)
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{
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void __iomem *base = l2x0_base;
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start &= ~(CACHE_LINE_SIZE - 1);
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__l2c210_op_pa_range(base + L2X0_CLEAN_LINE_PA, start, end);
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__l2c210_cache_sync(base);
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}
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static void l2c210_flush_range(unsigned long start, unsigned long end)
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{
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void __iomem *base = l2x0_base;
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start &= ~(CACHE_LINE_SIZE - 1);
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__l2c210_op_pa_range(base + L2X0_CLEAN_INV_LINE_PA, start, end);
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__l2c210_cache_sync(base);
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}
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static void l2c210_flush_all(void)
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{
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void __iomem *base = l2x0_base;
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BUG_ON(!irqs_disabled());
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__l2c_op_way(base + L2X0_CLEAN_INV_WAY);
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__l2c210_cache_sync(base);
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}
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static void l2c210_sync(void)
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{
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__l2c210_cache_sync(l2x0_base);
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}
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static void l2c210_resume(void)
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{
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void __iomem *base = l2x0_base;
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if (!(readl_relaxed(base + L2X0_CTRL) & L2X0_CTRL_EN))
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l2c_enable(base, l2x0_saved_regs.aux_ctrl, 1);
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}
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static const struct l2c_init_data l2c210_data __initconst = {
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.num_lock = 1,
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.enable = l2c_enable,
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.outer_cache = {
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.inv_range = l2c210_inv_range,
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.clean_range = l2c210_clean_range,
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.flush_range = l2c210_flush_range,
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.flush_all = l2c210_flush_all,
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.disable = l2c_disable,
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.sync = l2c210_sync,
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.resume = l2c210_resume,
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},
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};
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/*
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* L2C-310 specific code.
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*
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@ -623,6 +725,10 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
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data = &l2x0_init_fns;
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break;
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case L2X0_CACHE_ID_PART_L210:
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data = &l2c210_data;
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break;
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case L2X0_CACHE_ID_PART_L310:
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data = &l2c310_init_fns;
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break;
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@ -672,6 +778,21 @@ static void __init l2x0_of_parse(const struct device_node *np,
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*aux_mask &= ~mask;
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}
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static const struct l2c_init_data of_l2c210_data __initconst = {
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.num_lock = 1,
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.of_parse = l2x0_of_parse,
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.enable = l2c_enable,
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.outer_cache = {
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.inv_range = l2c210_inv_range,
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.clean_range = l2c210_clean_range,
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.flush_range = l2c210_flush_range,
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.flush_all = l2c210_flush_all,
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.disable = l2c_disable,
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.sync = l2c210_sync,
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.resume = l2c210_resume,
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},
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};
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static const struct l2c_init_data of_l2x0_data __initconst = {
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.of_parse = l2x0_of_parse,
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.enable = l2x0_enable,
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@ -1117,7 +1238,7 @@ static const struct l2c_init_data of_tauros3_data __initconst = {
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#define L2C_ID(name, fns) { .compatible = name, .data = (void *)&fns }
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static const struct of_device_id l2x0_ids[] __initconst = {
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L2C_ID("arm,l210-cache", of_l2x0_data),
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L2C_ID("arm,l210-cache", of_l2c210_data),
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L2C_ID("arm,l220-cache", of_l2x0_data),
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L2C_ID("arm,pl310-cache", of_pl310_data),
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L2C_ID("brcm,bcm11351-a2-pl310-cache", of_bcm_l2x0_data),
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