forked from Minki/linux
bnxt_en: Update firmware interface spec. to 1.8.1.4.
Flow APIs are added in this firmware interface. Signed-off-by: Michael Chan <michael.chan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Michael Chan
David S. Miller
parent
33b86ba057
commit
6a17eb27bf
@ -11,14 +11,14 @@
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#ifndef BNXT_HSI_H
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#define BNXT_HSI_H
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/* HSI and HWRM Specification 1.8.0 */
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/* HSI and HWRM Specification 1.8.1 */
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#define HWRM_VERSION_MAJOR 1
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#define HWRM_VERSION_MINOR 8
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#define HWRM_VERSION_UPDATE 0
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#define HWRM_VERSION_UPDATE 1
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#define HWRM_VERSION_RSVD 0 /* non-zero means beta version */
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#define HWRM_VERSION_RSVD 4 /* non-zero means beta version */
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#define HWRM_VERSION_STR "1.8.0.0"
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#define HWRM_VERSION_STR "1.8.1.4"
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/*
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* Following is the signature for HWRM message field that indicates not
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* applicable (All F's). Need to cast it the size of the field if needed.
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@ -946,6 +946,7 @@ struct hwrm_func_cfg_input {
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#define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_DISABLE 0x400UL
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#define FUNC_CFG_REQ_FLAGS_VIRT_MAC_PERSIST 0x800UL
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#define FUNC_CFG_REQ_FLAGS_NO_AUTOCLEAR_STATISTIC 0x1000UL
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#define FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x2000UL
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__le32 enables;
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#define FUNC_CFG_REQ_ENABLES_MTU 0x1UL
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#define FUNC_CFG_REQ_ENABLES_MRU 0x2UL
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@ -1972,7 +1973,12 @@ struct hwrm_port_phy_qcaps_output {
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#define PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED 0x1UL
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#define PORT_PHY_QCAPS_RESP_FLAGS_RSVD1_MASK 0xfeUL
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#define PORT_PHY_QCAPS_RESP_FLAGS_RSVD1_SFT 1
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u8 unused_0;
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u8 port_cnt;
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#define PORT_PHY_QCAPS_RESP_PORT_CNT_UNKNOWN 0x0UL
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#define PORT_PHY_QCAPS_RESP_PORT_CNT_1 0x1UL
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#define PORT_PHY_QCAPS_RESP_PORT_CNT_2 0x2UL
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#define PORT_PHY_QCAPS_RESP_PORT_CNT_3 0x3UL
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#define PORT_PHY_QCAPS_RESP_PORT_CNT_4 0x4UL
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__le16 supported_speeds_force_mode;
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#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD 0x1UL
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#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MB 0x2UL
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@ -4407,6 +4413,164 @@ struct hwrm_cfa_ntuple_filter_cfg_output {
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u8 valid;
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};
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/* hwrm_cfa_flow_alloc */
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/* Input (128 bytes) */
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struct hwrm_cfa_flow_alloc_input {
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__le16 req_type;
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__le16 cmpl_ring;
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__le16 seq_id;
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__le16 target_id;
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__le64 resp_addr;
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__le16 flags;
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#define CFA_FLOW_ALLOC_REQ_FLAGS_TUNNEL 0x1UL
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#define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_MASK 0x6UL
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#define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_SFT 1
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#define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_NONE (0x0UL << 1)
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#define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_ONE (0x1UL << 1)
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#define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO (0x2UL << 1)
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#define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_LAST CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO
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#define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_MASK 0x38UL
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#define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_SFT 3
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#define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_L2 (0x0UL << 3)
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#define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV4 (0x1UL << 3)
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#define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 (0x2UL << 3)
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#define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_LAST CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6
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__le16 src_fid;
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__le32 tunnel_handle;
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__le16 action_flags;
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#define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FWD 0x1UL
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#define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_RECYCLE 0x2UL
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#define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_DROP 0x4UL
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#define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_METER 0x8UL
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#define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL 0x10UL
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#define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_SRC 0x20UL
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#define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_DEST 0x40UL
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#define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_IPV4_ADDRESS 0x80UL
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#define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_L2_HEADER_REWRITE 0x100UL
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#define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TTL_DECREMENT 0x200UL
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__le16 dst_fid;
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__be16 l2_rewrite_vlan_tpid;
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__be16 l2_rewrite_vlan_tci;
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__le16 act_meter_id;
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__le16 ref_flow_handle;
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__be16 ethertype;
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__be16 outer_vlan_tci;
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__be16 dmac[3];
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__be16 inner_vlan_tci;
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__be16 smac[3];
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u8 ip_dst_mask_len;
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u8 ip_src_mask_len;
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__be32 ip_dst[4];
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__be32 ip_src[4];
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__be16 l4_src_port;
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__be16 l4_src_port_mask;
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__be16 l4_dst_port;
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__be16 l4_dst_port_mask;
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__be32 nat_ip_address[4];
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__be16 l2_rewrite_dmac[3];
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__be16 nat_port;
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__be16 l2_rewrite_smac[3];
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u8 ip_proto;
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u8 unused_0;
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};
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/* Output (16 bytes) */
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struct hwrm_cfa_flow_alloc_output {
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__le16 error_code;
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__le16 req_type;
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__le16 seq_id;
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__le16 resp_len;
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__le16 flow_handle;
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u8 unused_0;
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u8 unused_1;
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u8 unused_2;
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u8 unused_3;
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u8 unused_4;
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u8 valid;
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};
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/* hwrm_cfa_flow_free */
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/* Input (24 bytes) */
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struct hwrm_cfa_flow_free_input {
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__le16 req_type;
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__le16 cmpl_ring;
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__le16 seq_id;
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__le16 target_id;
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__le64 resp_addr;
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__le16 flow_handle;
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__le16 unused_0[3];
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};
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/* Output (32 bytes) */
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struct hwrm_cfa_flow_free_output {
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__le16 error_code;
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__le16 req_type;
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__le16 seq_id;
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__le16 resp_len;
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__le64 packet;
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__le64 byte;
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__le32 unused_0;
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u8 unused_1;
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u8 unused_2;
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u8 unused_3;
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u8 valid;
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};
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/* hwrm_cfa_flow_stats */
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/* Input (40 bytes) */
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struct hwrm_cfa_flow_stats_input {
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__le16 req_type;
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__le16 cmpl_ring;
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__le16 seq_id;
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__le16 target_id;
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__le64 resp_addr;
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__le16 num_flows;
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__le16 flow_handle_0;
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__le16 flow_handle_1;
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__le16 flow_handle_2;
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__le16 flow_handle_3;
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__le16 flow_handle_4;
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__le16 flow_handle_5;
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__le16 flow_handle_6;
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__le16 flow_handle_7;
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__le16 flow_handle_8;
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__le16 flow_handle_9;
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__le16 unused_0;
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};
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/* Output (176 bytes) */
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struct hwrm_cfa_flow_stats_output {
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__le16 error_code;
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__le16 req_type;
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__le16 seq_id;
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__le16 resp_len;
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__le64 packet_0;
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__le64 packet_1;
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__le64 packet_2;
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__le64 packet_3;
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__le64 packet_4;
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__le64 packet_5;
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__le64 packet_6;
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__le64 packet_7;
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__le64 packet_8;
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__le64 packet_9;
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__le64 byte_0;
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__le64 byte_1;
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__le64 byte_2;
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__le64 byte_3;
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__le64 byte_4;
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__le64 byte_5;
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__le64 byte_6;
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__le64 byte_7;
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__le64 byte_8;
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__le64 byte_9;
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__le32 unused_0;
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u8 unused_1;
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u8 unused_2;
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u8 unused_3;
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u8 valid;
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};
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/* hwrm_cfa_vfr_alloc */
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/* Input (32 bytes) */
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struct hwrm_cfa_vfr_alloc_input {
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@ -5534,11 +5698,15 @@ struct hwrm_selftest_qlist_output {
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#define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_LINK_TEST 0x2UL
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#define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_REGISTER_TEST 0x4UL
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#define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_MEMORY_TEST 0x8UL
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#define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_PCIE_EYE_TEST 0x10UL
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#define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_ETHERNET_EYE_TEST 0x20UL
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u8 offline_tests;
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#define SELFTEST_QLIST_RESP_OFFLINE_TESTS_NVM_TEST 0x1UL
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#define SELFTEST_QLIST_RESP_OFFLINE_TESTS_LINK_TEST 0x2UL
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#define SELFTEST_QLIST_RESP_OFFLINE_TESTS_REGISTER_TEST 0x4UL
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#define SELFTEST_QLIST_RESP_OFFLINE_TESTS_MEMORY_TEST 0x8UL
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#define SELFTEST_QLIST_RESP_OFFLINE_TESTS_PCIE_EYE_TEST 0x10UL
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#define SELFTEST_QLIST_RESP_OFFLINE_TESTS_ETHERNET_EYE_TEST 0x20UL
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u8 unused_0;
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__le16 test_timeout;
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u8 unused_1;
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@ -5566,6 +5734,8 @@ struct hwrm_selftest_exec_input {
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#define SELFTEST_EXEC_REQ_FLAGS_LINK_TEST 0x2UL
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#define SELFTEST_EXEC_REQ_FLAGS_REGISTER_TEST 0x4UL
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#define SELFTEST_EXEC_REQ_FLAGS_MEMORY_TEST 0x8UL
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#define SELFTEST_EXEC_REQ_FLAGS_PCIE_EYE_TEST 0x10UL
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#define SELFTEST_EXEC_REQ_FLAGS_ETHERNET_EYE_TEST 0x20UL
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u8 unused_0[7];
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};
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@ -5580,11 +5750,15 @@ struct hwrm_selftest_exec_output {
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#define SELFTEST_EXEC_RESP_REQUESTED_TESTS_LINK_TEST 0x2UL
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#define SELFTEST_EXEC_RESP_REQUESTED_TESTS_REGISTER_TEST 0x4UL
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#define SELFTEST_EXEC_RESP_REQUESTED_TESTS_MEMORY_TEST 0x8UL
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#define SELFTEST_EXEC_RESP_REQUESTED_TESTS_PCIE_EYE_TEST 0x10UL
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#define SELFTEST_EXEC_RESP_REQUESTED_TESTS_ETHERNET_EYE_TEST 0x20UL
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u8 test_success;
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#define SELFTEST_EXEC_RESP_TEST_SUCCESS_NVM_TEST 0x1UL
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#define SELFTEST_EXEC_RESP_TEST_SUCCESS_LINK_TEST 0x2UL
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#define SELFTEST_EXEC_RESP_TEST_SUCCESS_REGISTER_TEST 0x4UL
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#define SELFTEST_EXEC_RESP_TEST_SUCCESS_MEMORY_TEST 0x8UL
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#define SELFTEST_EXEC_RESP_TEST_SUCCESS_PCIE_EYE_TEST 0x10UL
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#define SELFTEST_EXEC_RESP_TEST_SUCCESS_ETHERNET_EYE_TEST 0x20UL
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__le16 unused_0[3];
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};
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@ -5767,6 +5941,7 @@ struct cmd_nums {
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#define HWRM_SELFTEST_QLIST (0x200UL)
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#define HWRM_SELFTEST_EXEC (0x201UL)
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#define HWRM_SELFTEST_IRQ (0x202UL)
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#define HWRM_SELFTEST_RETREIVE_EYE_DATA (0x203UL)
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#define HWRM_DBG_READ_DIRECT (0xff10UL)
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#define HWRM_DBG_READ_INDIRECT (0xff11UL)
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#define HWRM_DBG_WRITE_DIRECT (0xff12UL)
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@ -5984,6 +6159,7 @@ struct hwrm_struct_hdr {
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#define STRUCT_HDR_STRUCT_ID_LLDP_DEVICE 0x426UL
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#define STRUCT_HDR_STRUCT_ID_AFM_OPAQUE 0x1UL
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#define STRUCT_HDR_STRUCT_ID_PORT_DESCRIPTION 0xaUL
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#define STRUCT_HDR_STRUCT_ID_RSS_V2 0x64UL
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__le16 len;
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u8 version;
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u8 count;
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