forked from Minki/linux
PCI: qcom: Use bulk clk api and assert on error
Rework 2.1.0 revision to use bulk clk api and fix missing assert on reset_control_deassert error. Link: https://lore.kernel.org/r/20200615210608.21469-7-ansuelsmth@gmail.com Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
This commit is contained in:
Ansuel Smith
Lorenzo Pieralisi
parent
b11b8cc161
commit
6a114526af
@ -84,12 +84,9 @@
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#define DEVICE_TYPE_RC 0x4
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#define QCOM_PCIE_2_1_0_MAX_SUPPLY 3
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#define QCOM_PCIE_2_1_0_MAX_CLOCKS 5
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struct qcom_pcie_resources_2_1_0 {
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struct clk *iface_clk;
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struct clk *core_clk;
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struct clk *phy_clk;
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struct clk *aux_clk;
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struct clk *ref_clk;
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struct clk_bulk_data clks[QCOM_PCIE_2_1_0_MAX_CLOCKS];
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struct reset_control *pci_reset;
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struct reset_control *axi_reset;
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struct reset_control *ahb_reset;
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@ -237,25 +234,21 @@ static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie)
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if (ret)
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return ret;
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res->iface_clk = devm_clk_get(dev, "iface");
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if (IS_ERR(res->iface_clk))
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return PTR_ERR(res->iface_clk);
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res->clks[0].id = "iface";
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res->clks[1].id = "core";
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res->clks[2].id = "phy";
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res->clks[3].id = "aux";
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res->clks[4].id = "ref";
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res->core_clk = devm_clk_get(dev, "core");
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if (IS_ERR(res->core_clk))
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return PTR_ERR(res->core_clk);
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/* iface, core, phy are required */
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ret = devm_clk_bulk_get(dev, 3, res->clks);
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if (ret < 0)
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return ret;
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res->phy_clk = devm_clk_get(dev, "phy");
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if (IS_ERR(res->phy_clk))
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return PTR_ERR(res->phy_clk);
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res->aux_clk = devm_clk_get_optional(dev, "aux");
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if (IS_ERR(res->aux_clk))
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return PTR_ERR(res->aux_clk);
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res->ref_clk = devm_clk_get_optional(dev, "ref");
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if (IS_ERR(res->ref_clk))
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return PTR_ERR(res->ref_clk);
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/* aux, ref are optional */
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ret = devm_clk_bulk_get_optional(dev, 2, res->clks + 3);
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if (ret < 0)
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return ret;
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res->pci_reset = devm_reset_control_get_exclusive(dev, "pci");
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if (IS_ERR(res->pci_reset))
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@ -285,17 +278,13 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie)
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{
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struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
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clk_disable_unprepare(res->phy_clk);
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clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks);
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reset_control_assert(res->pci_reset);
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reset_control_assert(res->axi_reset);
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reset_control_assert(res->ahb_reset);
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reset_control_assert(res->por_reset);
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reset_control_assert(res->ext_reset);
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reset_control_assert(res->phy_reset);
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clk_disable_unprepare(res->iface_clk);
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clk_disable_unprepare(res->core_clk);
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clk_disable_unprepare(res->aux_clk);
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clk_disable_unprepare(res->ref_clk);
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regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
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}
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@ -313,36 +302,6 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
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return ret;
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}
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ret = reset_control_assert(res->ahb_reset);
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if (ret) {
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dev_err(dev, "cannot assert ahb reset\n");
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goto err_assert_ahb;
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}
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ret = clk_prepare_enable(res->iface_clk);
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if (ret) {
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dev_err(dev, "cannot prepare/enable iface clock\n");
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goto err_assert_ahb;
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}
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ret = clk_prepare_enable(res->core_clk);
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if (ret) {
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dev_err(dev, "cannot prepare/enable core clock\n");
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goto err_clk_core;
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}
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ret = clk_prepare_enable(res->aux_clk);
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if (ret) {
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dev_err(dev, "cannot prepare/enable aux clock\n");
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goto err_clk_aux;
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}
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ret = clk_prepare_enable(res->ref_clk);
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if (ret) {
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dev_err(dev, "cannot prepare/enable ref clock\n");
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goto err_clk_ref;
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}
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ret = reset_control_deassert(res->ahb_reset);
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if (ret) {
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dev_err(dev, "cannot deassert ahb reset\n");
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@ -352,9 +311,37 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
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ret = reset_control_deassert(res->ext_reset);
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if (ret) {
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dev_err(dev, "cannot deassert ext reset\n");
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goto err_deassert_ahb;
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goto err_deassert_ext;
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}
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ret = reset_control_deassert(res->phy_reset);
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if (ret) {
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dev_err(dev, "cannot deassert phy reset\n");
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goto err_deassert_phy;
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}
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ret = reset_control_deassert(res->pci_reset);
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if (ret) {
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dev_err(dev, "cannot deassert pci reset\n");
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goto err_deassert_pci;
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}
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ret = reset_control_deassert(res->por_reset);
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if (ret) {
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dev_err(dev, "cannot deassert por reset\n");
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goto err_deassert_por;
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}
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ret = reset_control_deassert(res->axi_reset);
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if (ret) {
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dev_err(dev, "cannot deassert axi reset\n");
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goto err_deassert_axi;
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}
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ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks);
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if (ret)
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goto err_clks;
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/* enable PCIe clocks and resets */
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val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
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val &= ~BIT(0);
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@ -365,36 +352,6 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
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val |= BIT(16);
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writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK);
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ret = reset_control_deassert(res->phy_reset);
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if (ret) {
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dev_err(dev, "cannot deassert phy reset\n");
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return ret;
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}
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ret = reset_control_deassert(res->pci_reset);
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if (ret) {
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dev_err(dev, "cannot deassert pci reset\n");
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return ret;
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}
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ret = reset_control_deassert(res->por_reset);
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if (ret) {
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dev_err(dev, "cannot deassert por reset\n");
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return ret;
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}
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ret = reset_control_deassert(res->axi_reset);
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if (ret) {
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dev_err(dev, "cannot deassert axi reset\n");
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return ret;
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}
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ret = clk_prepare_enable(res->phy_clk);
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if (ret) {
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dev_err(dev, "cannot prepare/enable phy clock\n");
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goto err_deassert_ahb;
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}
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/* wait for clock acquisition */
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usleep_range(1000, 1500);
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@ -407,15 +364,19 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
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return 0;
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err_clks:
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reset_control_assert(res->axi_reset);
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err_deassert_axi:
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reset_control_assert(res->por_reset);
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err_deassert_por:
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reset_control_assert(res->pci_reset);
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err_deassert_pci:
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reset_control_assert(res->phy_reset);
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err_deassert_phy:
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reset_control_assert(res->ext_reset);
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err_deassert_ext:
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reset_control_assert(res->ahb_reset);
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err_deassert_ahb:
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clk_disable_unprepare(res->ref_clk);
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err_clk_ref:
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clk_disable_unprepare(res->aux_clk);
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err_clk_aux:
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clk_disable_unprepare(res->core_clk);
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err_clk_core:
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clk_disable_unprepare(res->iface_clk);
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err_assert_ahb:
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regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
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return ret;
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