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MIPS: asm: stackframe: Do not preserve the HI/LO registers on MIPS R6

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The HI/LO registers have been removed from MIPS R6. Instructions
such as MULT and DIV have been replaced with a new pair of
instructions for the HI/LO operations for example:

MULT -> MUL, MUH
DIV -> DIV, MOD

So we avoid preserving the pre-R6 HI/LO registers in MIPS R6

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
This commit is contained in:
Leonid Yegoshin
2014-10-27 11:37:47 +00:00
committed by Markos Chandras
parent b840a82c54
commit 6a0e9865b9
1 changed files with 4 additions and 4 deletions
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8
arch/mips/include/asm/stackframe.h
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@@ -40,7 +40,7 @@
LONG_S v1, PT_HI(sp) LONG_S v1, PT_HI(sp)
mflhxu v1 mflhxu v1
LONG_S v1, PT_ACX(sp) LONG_S v1, PT_ACX(sp)
#else #elif !defined(CONFIG_CPU_MIPSR6)
mfhi v1 mfhi v1
#endif #endif
#ifdef CONFIG_32BIT #ifdef CONFIG_32BIT
@@ -50,7 +50,7 @@
LONG_S $10, PT_R10(sp) LONG_S $10, PT_R10(sp)
LONG_S $11, PT_R11(sp) LONG_S $11, PT_R11(sp)
LONG_S $12, PT_R12(sp) LONG_S $12, PT_R12(sp)
#ifndef CONFIG_CPU_HAS_SMARTMIPS #if !defined(CONFIG_CPU_HAS_SMARTMIPS) && !defined(CONFIG_CPU_MIPSR6)
LONG_S v1, PT_HI(sp) LONG_S v1, PT_HI(sp)
mflo v1 mflo v1
#endif #endif
@@ -58,7 +58,7 @@
LONG_S $14, PT_R14(sp) LONG_S $14, PT_R14(sp)
LONG_S $15, PT_R15(sp) LONG_S $15, PT_R15(sp)
LONG_S $24, PT_R24(sp) LONG_S $24, PT_R24(sp)
#ifndef CONFIG_CPU_HAS_SMARTMIPS #if !defined(CONFIG_CPU_HAS_SMARTMIPS) && !defined(CONFIG_CPU_MIPSR6)
LONG_S v1, PT_LO(sp) LONG_S v1, PT_LO(sp)
#endif #endif
#ifdef CONFIG_CPU_CAVIUM_OCTEON #ifdef CONFIG_CPU_CAVIUM_OCTEON
@@ -226,7 +226,7 @@
mtlhx $24 mtlhx $24
LONG_L $24, PT_LO(sp) LONG_L $24, PT_LO(sp)
mtlhx $24 mtlhx $24
#else #elif !defined(CONFIG_CPU_MIPSR6)
LONG_L $24, PT_LO(sp) LONG_L $24, PT_LO(sp)
mtlo $24 mtlo $24
LONG_L $24, PT_HI(sp) LONG_L $24, PT_HI(sp)