forked from Minki/linux
Merge git://git.infradead.org/iommu-2.6
* git://git.infradead.org/iommu-2.6: intel-iommu: fix superpage support in pfn_to_dma_pte() intel-iommu: set iommu_superpage on VM domains to lowest common denominator intel-iommu: fix return value of iommu_unmap() API MAINTAINERS: Update VT-d entry for drivers/pci -> drivers/iommu move intel-iommu: Export a flag indicating that the IOMMU is used for iGFX. intel-iommu: Workaround IOTLB hang on Ironlake GPU intel-iommu: Fix AB-BA lockdep report
This commit is contained in:
Linus Torvalds
commit
6a0596583f
@ -3313,7 +3313,7 @@ M: David Woodhouse <dwmw2@infradead.org>
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L: iommu@lists.linux-foundation.org
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T: git git://git.infradead.org/iommu-2.6.git
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S: Supported
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F: drivers/pci/intel-iommu.c
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F: drivers/iommu/intel-iommu.c
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F: include/linux/intel-iommu.h
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INTEL IOP-ADMA DMA DRIVER
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@ -306,6 +306,11 @@ static inline bool dma_pte_present(struct dma_pte *pte)
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return (pte->val & 3) != 0;
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}
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static inline bool dma_pte_superpage(struct dma_pte *pte)
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{
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return (pte->val & (1 << 7));
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}
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static inline int first_pte_in_page(struct dma_pte *pte)
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{
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return !((unsigned long)pte & ~VTD_PAGE_MASK);
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@ -404,6 +409,9 @@ static int dmar_forcedac;
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static int intel_iommu_strict;
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static int intel_iommu_superpage = 1;
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int intel_iommu_gfx_mapped;
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EXPORT_SYMBOL_GPL(intel_iommu_gfx_mapped);
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#define DUMMY_DEVICE_DOMAIN_INFO ((struct device_domain_info *)(-1))
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static DEFINE_SPINLOCK(device_domain_lock);
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static LIST_HEAD(device_domain_list);
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@ -577,17 +585,18 @@ static void domain_update_iommu_snooping(struct dmar_domain *domain)
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static void domain_update_iommu_superpage(struct dmar_domain *domain)
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{
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int i, mask = 0xf;
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struct dmar_drhd_unit *drhd;
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struct intel_iommu *iommu = NULL;
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int mask = 0xf;
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if (!intel_iommu_superpage) {
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domain->iommu_superpage = 0;
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return;
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}
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domain->iommu_superpage = 4; /* 1TiB */
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for_each_set_bit(i, &domain->iommu_bmp, g_num_of_iommus) {
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mask |= cap_super_page_val(g_iommus[i]->cap);
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/* set iommu_superpage to the smallest common denominator */
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for_each_active_iommu(iommu, drhd) {
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mask &= cap_super_page_val(iommu->cap);
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if (!mask) {
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break;
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}
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@ -730,29 +739,23 @@ out:
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}
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static struct dma_pte *pfn_to_dma_pte(struct dmar_domain *domain,
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unsigned long pfn, int large_level)
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unsigned long pfn, int target_level)
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{
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int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
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struct dma_pte *parent, *pte = NULL;
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int level = agaw_to_level(domain->agaw);
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int offset, target_level;
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int offset;
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BUG_ON(!domain->pgd);
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BUG_ON(addr_width < BITS_PER_LONG && pfn >> addr_width);
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parent = domain->pgd;
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/* Search pte */
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if (!large_level)
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target_level = 1;
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else
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target_level = large_level;
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while (level > 0) {
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void *tmp_page;
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offset = pfn_level_offset(pfn, level);
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pte = &parent[offset];
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if (!large_level && (pte->val & DMA_PTE_LARGE_PAGE))
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if (!target_level && (dma_pte_superpage(pte) || !dma_pte_present(pte)))
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break;
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if (level == target_level)
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break;
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@ -816,13 +819,14 @@ static struct dma_pte *dma_pfn_level_pte(struct dmar_domain *domain,
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}
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/* clear last level pte, a tlb flush should be followed */
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static void dma_pte_clear_range(struct dmar_domain *domain,
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static int dma_pte_clear_range(struct dmar_domain *domain,
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unsigned long start_pfn,
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unsigned long last_pfn)
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{
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int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
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unsigned int large_page = 1;
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struct dma_pte *first_pte, *pte;
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int order;
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BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
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BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
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@ -846,6 +850,9 @@ static void dma_pte_clear_range(struct dmar_domain *domain,
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(void *)pte - (void *)first_pte);
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} while (start_pfn && start_pfn <= last_pfn);
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order = (large_page - 1) * 9;
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return order;
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}
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/* free page table pages. last level pte should already be cleared */
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@ -3226,9 +3233,6 @@ static void __init init_no_remapping_devices(void)
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}
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}
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if (dmar_map_gfx)
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return;
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for_each_drhd_unit(drhd) {
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int i;
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if (drhd->ignored || drhd->include_all)
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@ -3236,18 +3240,23 @@ static void __init init_no_remapping_devices(void)
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for (i = 0; i < drhd->devices_cnt; i++)
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if (drhd->devices[i] &&
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!IS_GFX_DEVICE(drhd->devices[i]))
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!IS_GFX_DEVICE(drhd->devices[i]))
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break;
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if (i < drhd->devices_cnt)
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continue;
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/* bypass IOMMU if it is just for gfx devices */
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drhd->ignored = 1;
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for (i = 0; i < drhd->devices_cnt; i++) {
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if (!drhd->devices[i])
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continue;
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drhd->devices[i]->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO;
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/* This IOMMU has *only* gfx devices. Either bypass it or
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set the gfx_mapped flag, as appropriate */
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if (dmar_map_gfx) {
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intel_iommu_gfx_mapped = 1;
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} else {
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drhd->ignored = 1;
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for (i = 0; i < drhd->devices_cnt; i++) {
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if (!drhd->devices[i])
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continue;
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drhd->devices[i]->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO;
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}
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}
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}
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}
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@ -3568,6 +3577,8 @@ static void domain_remove_one_dev_info(struct dmar_domain *domain,
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found = 1;
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}
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spin_unlock_irqrestore(&device_domain_lock, flags);
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if (found == 0) {
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unsigned long tmp_flags;
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spin_lock_irqsave(&domain->iommu_lock, tmp_flags);
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@ -3584,8 +3595,6 @@ static void domain_remove_one_dev_info(struct dmar_domain *domain,
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spin_unlock_irqrestore(&iommu->lock, tmp_flags);
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}
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}
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spin_unlock_irqrestore(&device_domain_lock, flags);
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}
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static void vm_domain_remove_all_dev_info(struct dmar_domain *domain)
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@ -3739,6 +3748,7 @@ static int intel_iommu_domain_init(struct iommu_domain *domain)
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vm_domain_exit(dmar_domain);
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return -ENOMEM;
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}
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domain_update_iommu_cap(dmar_domain);
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domain->priv = dmar_domain;
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return 0;
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@ -3864,14 +3874,15 @@ static int intel_iommu_unmap(struct iommu_domain *domain,
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{
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struct dmar_domain *dmar_domain = domain->priv;
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size_t size = PAGE_SIZE << gfp_order;
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int order;
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dma_pte_clear_range(dmar_domain, iova >> VTD_PAGE_SHIFT,
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order = dma_pte_clear_range(dmar_domain, iova >> VTD_PAGE_SHIFT,
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(iova + size - 1) >> VTD_PAGE_SHIFT);
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if (dmar_domain->max_addr == iova + size)
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dmar_domain->max_addr = iova;
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return gfp_order;
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return order;
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}
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static phys_addr_t intel_iommu_iova_to_phys(struct iommu_domain *domain,
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@ -3950,7 +3961,11 @@ static void __devinit quirk_calpella_no_shadow_gtt(struct pci_dev *dev)
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if (!(ggc & GGC_MEMORY_VT_ENABLED)) {
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printk(KERN_INFO "DMAR: BIOS has allocated no shadow GTT; disabling IOMMU for graphics\n");
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dmar_map_gfx = 0;
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}
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} else if (dmar_map_gfx) {
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/* we have to ensure the gfx device is idle before we flush */
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printk(KERN_INFO "DMAR: Disabling batched IOTLB flush on Ironlake\n");
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intel_iommu_strict = 1;
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}
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0040, quirk_calpella_no_shadow_gtt);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0044, quirk_calpella_no_shadow_gtt);
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