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clk: samsung: exynos5433: Add clocks for CMU_CAM0 domain

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This patch adds the mux/divider/gate clocks for CMU_CAM0 domain which
generates the clocks for MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1} IPs.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This commit is contained in:
Chanwoo Choi
2015-02-03 09:13:55 +09:00
committed by Sylwester Nawrocki
parent 8e46c4b84f
commit 6958f22f39
3 changed files with 670 additions and 1 deletions
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146
include/dt-bindings/clock/exynos5433.h
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@@ -118,6 +118,9 @@
#define CLK_DIV_ACLK_MSCL_400 145
#define CLK_DIV_ACLK_ISP_DIS_400 146
#define CLK_DIV_ACLK_ISP_400 147
#define CLK_DIV_ACLK_CAM0_333 148
#define CLK_DIV_ACLK_CAM0_400 149
#define CLK_DIV_ACLK_CAM0_552 150
#define CLK_ACLK_PERIC_66 200
#define CLK_ACLK_PERIS_66 201
@@ -159,8 +162,11 @@
#define CLK_ACLK_HEVC_400 237
#define CLK_ACLK_ISP_DIS_400 238
#define CLK_ACLK_ISP_400 239
#define CLK_ACLK_CAM0_333 240
#define CLK_ACLK_CAM0_400 241
#define CLK_ACLK_CAM0_552 242
#define TOP_NR_CLK 240
#define TOP_NR_CLK 243
/* CMU_CPIF */
#define CLK_FOUT_MPHY_PLL 1
@@ -1113,4 +1119,142 @@
#define ISP_NR_CLK 78
/* CMU_CAM0 */
#define CLK_PHYCLK_RXBYTEECLKHS0_S4_PHY 1
#define CLK_PHYCLK_RXBYTEECLKHS0_S2A_PHY 2
#define CLK_MOUT_ACLK_CAM0_333_USER 3
#define CLK_MOUT_ACLK_CAM0_400_USER 4
#define CLK_MOUT_ACLK_CAM0_552_USER 5
#define CLK_MOUT_PHYCLK_RXBYTECLKHS0_S4_USER 6
#define CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2A_USER 7
#define CLK_MOUT_ACLK_LITE_D_B 8
#define CLK_MOUT_ACLK_LITE_D_A 9
#define CLK_MOUT_ACLK_LITE_B_B 10
#define CLK_MOUT_ACLK_LITE_B_A 11
#define CLK_MOUT_ACLK_LITE_A_B 12
#define CLK_MOUT_ACLK_LITE_A_A 13
#define CLK_MOUT_ACLK_CAM0_400 14
#define CLK_MOUT_ACLK_CSIS1_B 15
#define CLK_MOUT_ACLK_CSIS1_A 16
#define CLK_MOUT_ACLK_CSIS0_B 17
#define CLK_MOUT_ACLK_CSIS0_A 18
#define CLK_MOUT_ACLK_3AA1_B 19
#define CLK_MOUT_ACLK_3AA1_A 20
#define CLK_MOUT_ACLK_3AA0_B 21
#define CLK_MOUT_ACLK_3AA0_A 22
#define CLK_MOUT_SCLK_LITE_FREECNT_C 23
#define CLK_MOUT_SCLK_LITE_FREECNT_B 24
#define CLK_MOUT_SCLK_LITE_FREECNT_A 25
#define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_B 26
#define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_A 27
#define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_B 28
#define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_A 29
#define CLK_DIV_PCLK_CAM0_50 30
#define CLK_DIV_ACLK_CAM0_200 31
#define CLK_DIV_ACLK_CAM0_BUS_400 32
#define CLK_DIV_PCLK_LITE_D 33
#define CLK_DIV_ACLK_LITE_D 34
#define CLK_DIV_PCLK_LITE_B 35
#define CLK_DIV_ACLK_LITE_B 36
#define CLK_DIV_PCLK_LITE_A 37
#define CLK_DIV_ACLK_LITE_A 38
#define CLK_DIV_ACLK_CSIS1 39
#define CLK_DIV_ACLK_CSIS0 40
#define CLK_DIV_PCLK_3AA1 41
#define CLK_DIV_ACLK_3AA1 42
#define CLK_DIV_PCLK_3AA0 43
#define CLK_DIV_ACLK_3AA0 44
#define CLK_DIV_SCLK_PIXELASYNC_LITE_C 45
#define CLK_DIV_PCLK_PIXELASYNC_LITE_C 46
#define CLK_DIV_SCLK_PIXELASYNC_LITE_C_INIT 47
#define CLK_ACLK_CSIS1 50
#define CLK_ACLK_CSIS0 51
#define CLK_ACLK_3AA1 52
#define CLK_ACLK_3AA0 53
#define CLK_ACLK_LITE_D 54
#define CLK_ACLK_LITE_B 55
#define CLK_ACLK_LITE_A 56
#define CLK_ACLK_AHBSYNCDN 57
#define CLK_ACLK_AXIUS_LITE_D 58
#define CLK_ACLK_AXIUS_LITE_B 59
#define CLK_ACLK_AXIUS_LITE_A 60
#define CLK_ACLK_ASYNCAPBM_3AA1 61
#define CLK_ACLK_ASYNCAPBS_3AA1 62
#define CLK_ACLK_ASYNCAPBM_3AA0 63
#define CLK_ACLK_ASYNCAPBS_3AA0 64
#define CLK_ACLK_ASYNCAPBM_LITE_D 65
#define CLK_ACLK_ASYNCAPBS_LITE_D 66
#define CLK_ACLK_ASYNCAPBM_LITE_B 67
#define CLK_ACLK_ASYNCAPBS_LITE_B 68
#define CLK_ACLK_ASYNCAPBM_LITE_A 69
#define CLK_ACLK_ASYNCAPBS_LITE_A 70
#define CLK_ACLK_ASYNCAXIM_ISP0P 71
#define CLK_ACLK_ASYNCAXIM_3AA1 72
#define CLK_ACLK_ASYNCAXIS_3AA1 73
#define CLK_ACLK_ASYNCAXIM_3AA0 74
#define CLK_ACLK_ASYNCAXIS_3AA0 75
#define CLK_ACLK_ASYNCAXIM_LITE_D 76
#define CLK_ACLK_ASYNCAXIS_LITE_D 77
#define CLK_ACLK_ASYNCAXIM_LITE_B 78
#define CLK_ACLK_ASYNCAXIS_LITE_B 79
#define CLK_ACLK_ASYNCAXIM_LITE_A 80
#define CLK_ACLK_ASYNCAXIS_LITE_A 81
#define CLK_ACLK_AHB2APB_ISPSFRP 82
#define CLK_ACLK_AXI2APB_ISP0P 83
#define CLK_ACLK_AXI2AHB_ISP0P 84
#define CLK_ACLK_XIU_IS0X 85
#define CLK_ACLK_XIU_ISP0EX 86
#define CLK_ACLK_CAM0NP_276 87
#define CLK_ACLK_CAM0ND_400 88
#define CLK_ACLK_SMMU_3AA1 89
#define CLK_ACLK_SMMU_3AA0 90
#define CLK_ACLK_SMMU_LITE_D 91
#define CLK_ACLK_SMMU_LITE_B 92
#define CLK_ACLK_SMMU_LITE_A 93
#define CLK_ACLK_BTS_3AA1 94
#define CLK_ACLK_BTS_3AA0 95
#define CLK_ACLK_BTS_LITE_D 96
#define CLK_ACLK_BTS_LITE_B 97
#define CLK_ACLK_BTS_LITE_A 98
#define CLK_PCLK_SMMU_3AA1 99
#define CLK_PCLK_SMMU_3AA0 100
#define CLK_PCLK_SMMU_LITE_D 101
#define CLK_PCLK_SMMU_LITE_B 102
#define CLK_PCLK_SMMU_LITE_A 103
#define CLK_PCLK_BTS_3AA1 104
#define CLK_PCLK_BTS_3AA0 105
#define CLK_PCLK_BTS_LITE_D 106
#define CLK_PCLK_BTS_LITE_B 107
#define CLK_PCLK_BTS_LITE_A 108
#define CLK_PCLK_ASYNCAXI_CAM1 109
#define CLK_PCLK_ASYNCAXI_3AA1 110
#define CLK_PCLK_ASYNCAXI_3AA0 111
#define CLK_PCLK_ASYNCAXI_LITE_D 112
#define CLK_PCLK_ASYNCAXI_LITE_B 113
#define CLK_PCLK_ASYNCAXI_LITE_A 114
#define CLK_PCLK_PMU_CAM0 115
#define CLK_PCLK_SYSREG_CAM0 116
#define CLK_PCLK_CMU_CAM0_LOCAL 117
#define CLK_PCLK_CSIS1 118
#define CLK_PCLK_CSIS0 119
#define CLK_PCLK_3AA1 120
#define CLK_PCLK_3AA0 121
#define CLK_PCLK_LITE_D 122
#define CLK_PCLK_LITE_B 123
#define CLK_PCLK_LITE_A 124
#define CLK_PHYCLK_RXBYTECLKHS0_S4 125
#define CLK_PHYCLK_RXBYTECLKHS0_S2A 126
#define CLK_SCLK_LITE_FREECNT 127
#define CLK_SCLK_PIXELASYNCM_3AA1 128
#define CLK_SCLK_PIXELASYNCM_3AA0 129
#define CLK_SCLK_PIXELASYNCS_3AA0 130
#define CLK_SCLK_PIXELASYNCM_LITE_C 131
#define CLK_SCLK_PIXELASYNCM_LITE_C_INIT 132
#define CLK_SCLK_PIXELASYNCS_LITE_C_INIT 133
#define CAM0_NR_CLK 134
#endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */