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drm/i915: fix pch_nop support

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This was accidentally broken in the south error interrupt handling
work:

commit 8664281b64
Author: Paulo Zanoni <paulo.r.zanoni@intel.com>
Date:   Fri Apr 12 17:57:57 2013 -0300

    drm/i915: report Gen5+ CPU and PCH FIFO underruns

Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Daniel Vetter 2013-05-29 21:43:05 +02:00
parent 9a8a2213a7
commit 692a04cf77
1 changed files with 3 additions and 3 deletions
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6
drivers/gpu/drm/i915/i915_irq.c
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@ -2551,6 +2551,9 @@ static void ibx_irq_postinstall(struct drm_device *dev)
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
u32 mask;
if (HAS_PCH_NOP(dev))
return;
if (HAS_PCH_IBX(dev)) {
mask = SDE_GMBUS | SDE_AUX_MASK | SDE_TRANSB_FIFO_UNDER |
SDE_TRANSA_FIFO_UNDER | SDE_POISON;
@ -2560,9 +2563,6 @@ static void ibx_irq_postinstall(struct drm_device *dev)
I915_WRITE(SERR_INT, I915_READ(SERR_INT));
}
if (HAS_PCH_NOP(dev))
return;
I915_WRITE(SDEIIR, I915_READ(SDEIIR));
I915_WRITE(SDEIMR, ~mask);
}