forked from Minki/linux
RDMA/hns: Add FRMR support for hip08
This patch adds fast register physical memory region (FRMR) support for hip08. Signed-off-by: Yixian Liu <liuyixian@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
This commit is contained in:
parent
5df9509949
commit
68a997c5d2
@ -88,8 +88,11 @@
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#define BITMAP_RR 1
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#define MR_TYPE_MR 0x00
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#define MR_TYPE_FRMR 0x01
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#define MR_TYPE_DMA 0x03
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#define HNS_ROCE_FRMR_MAX_PA 512
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#define PKEY_ID 0xffff
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#define GUID_LEN 8
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#define NODE_DESC_SIZE 64
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@ -194,6 +197,7 @@ enum {
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HNS_ROCE_CAP_FLAG_RECORD_DB = BIT(3),
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HNS_ROCE_CAP_FLAG_SQ_RECORD_DB = BIT(4),
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HNS_ROCE_CAP_FLAG_MW = BIT(7),
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HNS_ROCE_CAP_FLAG_FRMR = BIT(8),
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HNS_ROCE_CAP_FLAG_ATOMIC = BIT(10),
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};
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@ -308,6 +312,7 @@ struct hns_roce_mr {
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u32 key; /* Key of MR */
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u32 pd; /* PD num of MR */
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u32 access;/* Access permission of MR */
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u32 npages;
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int enabled; /* MR's active status */
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int type; /* MR's register type */
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u64 *pbl_buf;/* MR's PBL space */
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@ -773,6 +778,7 @@ struct hns_roce_hw {
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struct hns_roce_mr *mr, int flags, u32 pdn,
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int mr_access_flags, u64 iova, u64 size,
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void *mb_buf);
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int (*frmr_write_mtpt)(void *mb_buf, struct hns_roce_mr *mr);
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int (*mw_write_mtpt)(void *mb_buf, struct hns_roce_mw *mw);
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void (*write_cqc)(struct hns_roce_dev *hr_dev,
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struct hns_roce_cq *hr_cq, void *mb_buf, u64 *mtts,
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@ -983,6 +989,10 @@ struct ib_mr *hns_roce_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
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int hns_roce_rereg_user_mr(struct ib_mr *mr, int flags, u64 start, u64 length,
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u64 virt_addr, int mr_access_flags, struct ib_pd *pd,
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struct ib_udata *udata);
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struct ib_mr *hns_roce_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type,
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u32 max_num_sg);
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int hns_roce_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents,
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unsigned int *sg_offset);
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int hns_roce_dereg_mr(struct ib_mr *ibmr);
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int hns_roce_hw2sw_mpt(struct hns_roce_dev *hr_dev,
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struct hns_roce_cmd_mailbox *mailbox,
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@ -54,6 +54,47 @@ static void set_data_seg_v2(struct hns_roce_v2_wqe_data_seg *dseg,
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dseg->len = cpu_to_le32(sg->length);
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}
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static void set_frmr_seg(struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
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struct hns_roce_wqe_frmr_seg *fseg,
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const struct ib_reg_wr *wr)
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{
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struct hns_roce_mr *mr = to_hr_mr(wr->mr);
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/* use ib_access_flags */
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roce_set_bit(rc_sq_wqe->byte_4,
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V2_RC_FRMR_WQE_BYTE_4_BIND_EN_S,
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wr->access & IB_ACCESS_MW_BIND ? 1 : 0);
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roce_set_bit(rc_sq_wqe->byte_4,
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V2_RC_FRMR_WQE_BYTE_4_ATOMIC_S,
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wr->access & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0);
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roce_set_bit(rc_sq_wqe->byte_4,
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V2_RC_FRMR_WQE_BYTE_4_RR_S,
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wr->access & IB_ACCESS_REMOTE_READ ? 1 : 0);
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roce_set_bit(rc_sq_wqe->byte_4,
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V2_RC_FRMR_WQE_BYTE_4_RW_S,
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wr->access & IB_ACCESS_REMOTE_WRITE ? 1 : 0);
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roce_set_bit(rc_sq_wqe->byte_4,
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V2_RC_FRMR_WQE_BYTE_4_LW_S,
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wr->access & IB_ACCESS_LOCAL_WRITE ? 1 : 0);
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/* Data structure reuse may lead to confusion */
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rc_sq_wqe->msg_len = cpu_to_le32(mr->pbl_ba & 0xffffffff);
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rc_sq_wqe->inv_key = cpu_to_le32(mr->pbl_ba >> 32);
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rc_sq_wqe->byte_16 = cpu_to_le32(wr->mr->length & 0xffffffff);
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rc_sq_wqe->byte_20 = cpu_to_le32(wr->mr->length >> 32);
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rc_sq_wqe->rkey = cpu_to_le32(wr->key);
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rc_sq_wqe->va = cpu_to_le64(wr->mr->iova);
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fseg->pbl_size = cpu_to_le32(mr->pbl_size);
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roce_set_field(fseg->mode_buf_pg_sz,
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V2_RC_FRMR_WQE_BYTE_40_PBL_BUF_PG_SZ_M,
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V2_RC_FRMR_WQE_BYTE_40_PBL_BUF_PG_SZ_S,
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mr->pbl_buf_pg_sz + PG_SHIFT_OFFSET);
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roce_set_bit(fseg->mode_buf_pg_sz,
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V2_RC_FRMR_WQE_BYTE_40_BLK_MODE_S, 0);
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}
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static void set_atomic_seg(struct hns_roce_wqe_atomic_seg *aseg,
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const struct ib_atomic_wr *wr)
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{
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@ -192,6 +233,7 @@ static int hns_roce_v2_post_send(struct ib_qp *ibqp,
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struct hns_roce_v2_ud_send_wqe *ud_sq_wqe;
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struct hns_roce_v2_rc_send_wqe *rc_sq_wqe;
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struct hns_roce_qp *qp = to_hr_qp(ibqp);
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struct hns_roce_wqe_frmr_seg *fseg;
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struct device *dev = hr_dev->dev;
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struct hns_roce_v2_db sq_db;
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struct ib_qp_attr attr;
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@ -462,6 +504,11 @@ static int hns_roce_v2_post_send(struct ib_qp *ibqp,
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rc_sq_wqe->inv_key =
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cpu_to_le32(wr->ex.invalidate_rkey);
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break;
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case IB_WR_REG_MR:
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hr_op = HNS_ROCE_V2_WQE_OP_FAST_REG_PMR;
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fseg = wqe;
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set_frmr_seg(rc_sq_wqe, fseg, reg_wr(wr));
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break;
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case IB_WR_ATOMIC_CMP_AND_SWP:
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hr_op = HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP;
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rc_sq_wqe->rkey =
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@ -505,7 +552,7 @@ static int hns_roce_v2_post_send(struct ib_qp *ibqp,
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V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M,
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V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S,
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wr->num_sge);
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} else {
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} else if (wr->opcode != IB_WR_REG_MR) {
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ret = set_rwqe_data_seg(ibqp, wr, rc_sq_wqe,
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wqe, &sge_ind, bad_wr);
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if (ret)
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@ -1297,7 +1344,8 @@ static int hns_roce_v2_profile(struct hns_roce_dev *hr_dev)
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HNS_ROCE_CAP_FLAG_SQ_RECORD_DB;
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if (hr_dev->pci_dev->revision == 0x21)
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caps->flags |= HNS_ROCE_CAP_FLAG_MW;
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caps->flags |= HNS_ROCE_CAP_FLAG_MW |
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HNS_ROCE_CAP_FLAG_FRMR;
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caps->pkey_table_len[0] = 1;
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caps->gid_table_len[0] = HNS_ROCE_V2_GID_INDEX_NUM;
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@ -1865,6 +1913,48 @@ static int hns_roce_v2_rereg_write_mtpt(struct hns_roce_dev *hr_dev,
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return 0;
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}
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static int hns_roce_v2_frmr_write_mtpt(void *mb_buf, struct hns_roce_mr *mr)
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{
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struct hns_roce_v2_mpt_entry *mpt_entry;
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mpt_entry = mb_buf;
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memset(mpt_entry, 0, sizeof(*mpt_entry));
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roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M,
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V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_FREE);
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roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PBL_HOP_NUM_M,
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V2_MPT_BYTE_4_PBL_HOP_NUM_S, 1);
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roce_set_field(mpt_entry->byte_4_pd_hop_st,
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V2_MPT_BYTE_4_PBL_BA_PG_SZ_M,
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V2_MPT_BYTE_4_PBL_BA_PG_SZ_S,
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mr->pbl_ba_pg_sz + PG_SHIFT_OFFSET);
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roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M,
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V2_MPT_BYTE_4_PD_S, mr->pd);
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roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RA_EN_S, 1);
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roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_R_INV_EN_S, 1);
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roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_L_INV_EN_S, 1);
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roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_FRE_S, 1);
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roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_PA_S, 0);
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roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_MR_MW_S, 0);
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roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_BPD_S, 1);
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mpt_entry->pbl_size = cpu_to_le32(mr->pbl_size);
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mpt_entry->pbl_ba_l = cpu_to_le32(lower_32_bits(mr->pbl_ba >> 3));
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roce_set_field(mpt_entry->byte_48_mode_ba, V2_MPT_BYTE_48_PBL_BA_H_M,
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V2_MPT_BYTE_48_PBL_BA_H_S,
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upper_32_bits(mr->pbl_ba >> 3));
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roce_set_field(mpt_entry->byte_64_buf_pa1,
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V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M,
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V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S,
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mr->pbl_buf_pg_sz + PG_SHIFT_OFFSET);
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return 0;
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}
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static int hns_roce_v2_mw_write_mtpt(void *mb_buf, struct hns_roce_mw *mw)
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{
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struct hns_roce_v2_mpt_entry *mpt_entry;
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@ -2834,6 +2924,9 @@ static void modify_qp_reset_to_init(struct ib_qp *ibqp,
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roce_set_bit(qpc_mask->byte_172_sq_psn, V2_QPC_BYTE_172_MSG_RNR_FLG_S,
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0);
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roce_set_bit(context->byte_172_sq_psn, V2_QPC_BYTE_172_FRE_S, 1);
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roce_set_bit(qpc_mask->byte_172_sq_psn, V2_QPC_BYTE_172_FRE_S, 0);
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roce_set_field(qpc_mask->byte_176_msg_pktn,
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V2_QPC_BYTE_176_MSG_USE_PKTN_M,
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V2_QPC_BYTE_176_MSG_USE_PKTN_S, 0);
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@ -5259,6 +5352,7 @@ static const struct hns_roce_hw hns_roce_hw_v2 = {
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.set_mac = hns_roce_v2_set_mac,
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.write_mtpt = hns_roce_v2_write_mtpt,
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.rereg_write_mtpt = hns_roce_v2_rereg_write_mtpt,
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.frmr_write_mtpt = hns_roce_v2_frmr_write_mtpt,
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.mw_write_mtpt = hns_roce_v2_mw_write_mtpt,
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.write_cqc = hns_roce_v2_write_cqc,
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.set_hem = hns_roce_v2_set_hem,
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@ -886,6 +886,8 @@ struct hns_roce_v2_mpt_entry {
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#define V2_MPT_BYTE_8_MW_CNT_S 8
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#define V2_MPT_BYTE_8_MW_CNT_M GENMASK(31, 8)
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#define V2_MPT_BYTE_12_FRE_S 0
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#define V2_MPT_BYTE_12_PA_S 1
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#define V2_MPT_BYTE_12_MR_MW_S 4
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@ -1058,6 +1060,16 @@ struct hns_roce_v2_rc_send_wqe {
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#define V2_RC_SEND_WQE_BYTE_4_INLINE_S 12
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#define V2_RC_FRMR_WQE_BYTE_4_BIND_EN_S 19
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#define V2_RC_FRMR_WQE_BYTE_4_ATOMIC_S 20
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#define V2_RC_FRMR_WQE_BYTE_4_RR_S 21
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#define V2_RC_FRMR_WQE_BYTE_4_RW_S 22
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#define V2_RC_FRMR_WQE_BYTE_4_LW_S 23
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#define V2_RC_SEND_WQE_BYTE_16_XRC_SRQN_S 0
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#define V2_RC_SEND_WQE_BYTE_16_XRC_SRQN_M GENMASK(23, 0)
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@ -1067,6 +1079,16 @@ struct hns_roce_v2_rc_send_wqe {
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#define V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S 0
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#define V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M GENMASK(23, 0)
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struct hns_roce_wqe_frmr_seg {
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__le32 pbl_size;
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__le32 mode_buf_pg_sz;
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};
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#define V2_RC_FRMR_WQE_BYTE_40_PBL_BUF_PG_SZ_S 4
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#define V2_RC_FRMR_WQE_BYTE_40_PBL_BUF_PG_SZ_M GENMASK(7, 4)
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#define V2_RC_FRMR_WQE_BYTE_40_BLK_MODE_S 8
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struct hns_roce_v2_wqe_data_seg {
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__le32 len;
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__le32 lkey;
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@ -535,6 +535,12 @@ static int hns_roce_register_device(struct hns_roce_dev *hr_dev)
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(1ULL << IB_USER_VERBS_CMD_DEALLOC_MW);
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}
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/* FRMR */
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if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_FRMR) {
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ib_dev->alloc_mr = hns_roce_alloc_mr;
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ib_dev->map_mr_sg = hns_roce_map_mr_sg;
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}
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/* OTHERS */
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ib_dev->get_port_immutable = hns_roce_port_immutable;
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ib_dev->disassociate_ucontext = hns_roce_disassociate_ucontext;
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@ -329,7 +329,7 @@ static int hns_roce_mhop_alloc(struct hns_roce_dev *hr_dev, int npages,
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u64 bt_idx;
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u64 size;
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mhop_num = hr_dev->caps.pbl_hop_num;
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mhop_num = (mr->type == MR_TYPE_FRMR ? 1 : hr_dev->caps.pbl_hop_num);
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pbl_bt_sz = 1 << (hr_dev->caps.pbl_ba_pg_sz + PAGE_SHIFT);
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pbl_last_bt_num = (npages + pbl_bt_sz / 8 - 1) / (pbl_bt_sz / 8);
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@ -351,7 +351,7 @@ static int hns_roce_mhop_alloc(struct hns_roce_dev *hr_dev, int npages,
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mr->pbl_size = npages;
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mr->pbl_ba = mr->pbl_dma_addr;
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mr->pbl_hop_num = hr_dev->caps.pbl_hop_num;
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mr->pbl_hop_num = mhop_num;
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mr->pbl_ba_pg_sz = hr_dev->caps.pbl_ba_pg_sz;
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mr->pbl_buf_pg_sz = hr_dev->caps.pbl_buf_pg_sz;
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return 0;
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@ -511,7 +511,6 @@ static int hns_roce_mr_alloc(struct hns_roce_dev *hr_dev, u32 pd, u64 iova,
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mr->key = hw_index_to_key(index); /* MR key */
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if (size == ~0ull) {
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mr->type = MR_TYPE_DMA;
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mr->pbl_buf = NULL;
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mr->pbl_dma_addr = 0;
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/* PBL multi-hop addressing parameters */
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@ -522,7 +521,6 @@ static int hns_roce_mr_alloc(struct hns_roce_dev *hr_dev, u32 pd, u64 iova,
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mr->pbl_l1_dma_addr = NULL;
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mr->pbl_l0_dma_addr = 0;
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} else {
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mr->type = MR_TYPE_MR;
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if (!hr_dev->caps.pbl_hop_num) {
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mr->pbl_buf = dma_alloc_coherent(dev, npages * 8,
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&(mr->pbl_dma_addr),
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@ -548,9 +546,9 @@ static void hns_roce_mhop_free(struct hns_roce_dev *hr_dev,
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u32 mhop_num;
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u64 bt_idx;
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npages = ib_umem_page_count(mr->umem);
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npages = mr->pbl_size;
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pbl_bt_sz = 1 << (hr_dev->caps.pbl_ba_pg_sz + PAGE_SHIFT);
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mhop_num = hr_dev->caps.pbl_hop_num;
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mhop_num = (mr->type == MR_TYPE_FRMR) ? 1 : hr_dev->caps.pbl_hop_num;
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if (mhop_num == HNS_ROCE_HOP_NUM_0)
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return;
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@ -636,7 +634,8 @@ static void hns_roce_mr_free(struct hns_roce_dev *hr_dev,
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}
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if (mr->size != ~0ULL) {
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npages = ib_umem_page_count(mr->umem);
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if (mr->type == MR_TYPE_MR)
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npages = ib_umem_page_count(mr->umem);
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if (!hr_dev->caps.pbl_hop_num)
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dma_free_coherent(dev, (unsigned int)(npages * 8),
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@ -674,7 +673,10 @@ static int hns_roce_mr_enable(struct hns_roce_dev *hr_dev,
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goto err_table;
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}
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ret = hr_dev->hw->write_mtpt(mailbox->buf, mr, mtpt_idx);
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if (mr->type != MR_TYPE_FRMR)
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ret = hr_dev->hw->write_mtpt(mailbox->buf, mr, mtpt_idx);
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else
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ret = hr_dev->hw->frmr_write_mtpt(mailbox->buf, mr);
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if (ret) {
|
||||
dev_err(dev, "Write mtpt fail!\n");
|
||||
goto err_page;
|
||||
@ -855,6 +857,8 @@ struct ib_mr *hns_roce_get_dma_mr(struct ib_pd *pd, int acc)
|
||||
if (mr == NULL)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
mr->type = MR_TYPE_DMA;
|
||||
|
||||
/* Allocate memory region key */
|
||||
ret = hns_roce_mr_alloc(to_hr_dev(pd->device), to_hr_pd(pd)->pdn, 0,
|
||||
~0ULL, acc, 0, mr);
|
||||
@ -1031,6 +1035,8 @@ struct ib_mr *hns_roce_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
|
||||
}
|
||||
}
|
||||
|
||||
mr->type = MR_TYPE_MR;
|
||||
|
||||
ret = hns_roce_mr_alloc(hr_dev, to_hr_pd(pd)->pdn, virt_addr, length,
|
||||
access_flags, n, mr);
|
||||
if (ret)
|
||||
@ -1202,6 +1208,76 @@ int hns_roce_dereg_mr(struct ib_mr *ibmr)
|
||||
return ret;
|
||||
}
|
||||
|
||||
struct ib_mr *hns_roce_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type,
|
||||
u32 max_num_sg)
|
||||
{
|
||||
struct hns_roce_dev *hr_dev = to_hr_dev(pd->device);
|
||||
struct device *dev = hr_dev->dev;
|
||||
struct hns_roce_mr *mr;
|
||||
u64 length;
|
||||
u32 page_size;
|
||||
int ret;
|
||||
|
||||
page_size = 1 << (hr_dev->caps.pbl_buf_pg_sz + PAGE_SHIFT);
|
||||
length = max_num_sg * page_size;
|
||||
|
||||
if (mr_type != IB_MR_TYPE_MEM_REG)
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
||||
if (max_num_sg > HNS_ROCE_FRMR_MAX_PA) {
|
||||
dev_err(dev, "max_num_sg larger than %d\n",
|
||||
HNS_ROCE_FRMR_MAX_PA);
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
mr = kzalloc(sizeof(*mr), GFP_KERNEL);
|
||||
if (!mr)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
mr->type = MR_TYPE_FRMR;
|
||||
|
||||
/* Allocate memory region key */
|
||||
ret = hns_roce_mr_alloc(hr_dev, to_hr_pd(pd)->pdn, 0, length,
|
||||
0, max_num_sg, mr);
|
||||
if (ret)
|
||||
goto err_free;
|
||||
|
||||
ret = hns_roce_mr_enable(hr_dev, mr);
|
||||
if (ret)
|
||||
goto err_mr;
|
||||
|
||||
mr->ibmr.rkey = mr->ibmr.lkey = mr->key;
|
||||
mr->umem = NULL;
|
||||
|
||||
return &mr->ibmr;
|
||||
|
||||
err_mr:
|
||||
hns_roce_mr_free(to_hr_dev(pd->device), mr);
|
||||
|
||||
err_free:
|
||||
kfree(mr);
|
||||
return ERR_PTR(ret);
|
||||
}
|
||||
|
||||
static int hns_roce_set_page(struct ib_mr *ibmr, u64 addr)
|
||||
{
|
||||
struct hns_roce_mr *mr = to_hr_mr(ibmr);
|
||||
|
||||
mr->pbl_buf[mr->npages++] = cpu_to_le64(addr);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int hns_roce_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents,
|
||||
unsigned int *sg_offset)
|
||||
{
|
||||
struct hns_roce_mr *mr = to_hr_mr(ibmr);
|
||||
|
||||
mr->npages = 0;
|
||||
|
||||
return ib_sg_to_pages(ibmr, sg, sg_nents, sg_offset, hns_roce_set_page);
|
||||
}
|
||||
|
||||
static void hns_roce_mw_free(struct hns_roce_dev *hr_dev,
|
||||
struct hns_roce_mw *mw)
|
||||
{
|
||||
|
Loading…
Reference in New Issue
Block a user