brcmsmac: remove some pmu functions and use the bcma equivalents
This removes the following functions: si_pmu_chipcontrol() => bcma_chipco_chipctl_maskset() si_pmu_regcontrol() => bcma_chipco_regctl_maskset() si_pmu_pllcontrol() => bcma_chipco_pll_maskset() si_pmu_pllupd() => bcma_cc_set32() si_pmu_alp_clock() => bcma_chipco_get_alp_clock() This also removed the sih member from struct shared_phy. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
parent
ca84a6c5fb
commit
689b66cb53
@ -198,8 +198,6 @@ u16 read_radio_reg(struct brcms_phy *pi, u16 addr)
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void write_radio_reg(struct brcms_phy *pi, u16 addr, u16 val)
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void write_radio_reg(struct brcms_phy *pi, u16 addr, u16 val)
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{
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{
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struct si_info *sii = container_of(pi->sh->sih, struct si_info, pub);
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if ((D11REV_GE(pi->sh->corerev, 24)) ||
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if ((D11REV_GE(pi->sh->corerev, 24)) ||
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(D11REV_IS(pi->sh->corerev, 22)
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(D11REV_IS(pi->sh->corerev, 22)
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&& (pi->pubpi.phy_type != PHY_TYPE_SSN))) {
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&& (pi->pubpi.phy_type != PHY_TYPE_SSN))) {
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@ -211,7 +209,7 @@ void write_radio_reg(struct brcms_phy *pi, u16 addr, u16 val)
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bcma_write16(pi->d11core, D11REGOFFS(phy4wdatalo), val);
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bcma_write16(pi->d11core, D11REGOFFS(phy4wdatalo), val);
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}
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}
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if ((sii->icbus->hosttype == BCMA_HOSTTYPE_PCI) &&
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if ((pi->d11core->bus->hosttype == BCMA_HOSTTYPE_PCI) &&
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(++pi->phy_wreg >= pi->phy_wreg_limit)) {
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(++pi->phy_wreg >= pi->phy_wreg_limit)) {
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(void)bcma_read32(pi->d11core, D11REGOFFS(maccontrol));
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(void)bcma_read32(pi->d11core, D11REGOFFS(maccontrol));
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pi->phy_wreg = 0;
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pi->phy_wreg = 0;
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@ -297,10 +295,8 @@ void write_phy_reg(struct brcms_phy *pi, u16 addr, u16 val)
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if (addr == 0x72)
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if (addr == 0x72)
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(void)bcma_read16(pi->d11core, D11REGOFFS(phyregdata));
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(void)bcma_read16(pi->d11core, D11REGOFFS(phyregdata));
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#else
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#else
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struct si_info *sii = container_of(pi->sh->sih, struct si_info, pub);
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bcma_write32(pi->d11core, D11REGOFFS(phyregaddr), addr | (val << 16));
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bcma_write32(pi->d11core, D11REGOFFS(phyregaddr), addr | (val << 16));
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if ((sii->icbus->hosttype == BCMA_HOSTTYPE_PCI) &&
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if ((pi->d11core->bus->hosttype == BCMA_HOSTTYPE_PCI) &&
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(++pi->phy_wreg >= pi->phy_wreg_limit)) {
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(++pi->phy_wreg >= pi->phy_wreg_limit)) {
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pi->phy_wreg = 0;
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pi->phy_wreg = 0;
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(void)bcma_read16(pi->d11core, D11REGOFFS(phyversion));
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(void)bcma_read16(pi->d11core, D11REGOFFS(phyversion));
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@ -374,7 +370,6 @@ struct shared_phy *wlc_phy_shared_attach(struct shared_phy_params *shp)
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if (sh == NULL)
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if (sh == NULL)
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return NULL;
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return NULL;
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sh->sih = shp->sih;
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sh->physhim = shp->physhim;
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sh->physhim = shp->physhim;
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sh->unit = shp->unit;
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sh->unit = shp->unit;
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sh->corerev = shp->corerev;
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sh->corerev = shp->corerev;
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@ -2911,29 +2906,24 @@ void wlc_lcnphy_epa_switch(struct brcms_phy *pi, bool mode)
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mod_phy_reg(pi, 0x44c, (0x1 << 2), (1) << 2);
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mod_phy_reg(pi, 0x44c, (0x1 << 2), (1) << 2);
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}
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}
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ai_cc_reg(pi->sh->sih,
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offsetof(struct chipcregs, gpiocontrol),
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bcma_chipco_gpio_control(&pi->d11core->bus->drv_cc,
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~0x0, 0x0);
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0x0, 0x0);
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ai_cc_reg(pi->sh->sih,
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bcma_chipco_gpio_out(&pi->d11core->bus->drv_cc,
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offsetof(struct chipcregs, gpioout),
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~0x40, 0x40);
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0x40, 0x40);
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bcma_chipco_gpio_outen(&pi->d11core->bus->drv_cc,
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ai_cc_reg(pi->sh->sih,
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~0x40, 0x40);
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offsetof(struct chipcregs, gpioouten),
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0x40, 0x40);
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} else {
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} else {
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mod_phy_reg(pi, 0x44c, (0x1 << 2), (0) << 2);
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mod_phy_reg(pi, 0x44c, (0x1 << 2), (0) << 2);
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mod_phy_reg(pi, 0x44d, (0x1 << 2), (0) << 2);
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mod_phy_reg(pi, 0x44d, (0x1 << 2), (0) << 2);
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ai_cc_reg(pi->sh->sih,
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bcma_chipco_gpio_out(&pi->d11core->bus->drv_cc,
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offsetof(struct chipcregs, gpioout),
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~0x40, 0x00);
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0x40, 0x00);
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bcma_chipco_gpio_outen(&pi->d11core->bus->drv_cc,
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ai_cc_reg(pi->sh->sih,
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~0x40, 0x00);
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offsetof(struct chipcregs, gpioouten),
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bcma_chipco_gpio_control(&pi->d11core->bus->drv_cc,
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0x40, 0x0);
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0x0, 0x40);
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ai_cc_reg(pi->sh->sih,
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offsetof(struct chipcregs, gpiocontrol),
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~0x0, 0x40);
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}
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}
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}
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}
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}
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}
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@ -488,7 +488,6 @@ struct lcnphy_cal_results {
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struct shared_phy {
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struct shared_phy {
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struct brcms_phy *phy_head;
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struct brcms_phy *phy_head;
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uint unit;
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uint unit;
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struct si_pub *sih;
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struct phy_shim_info *physhim;
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struct phy_shim_info *physhim;
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uint corerev;
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uint corerev;
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u32 machwcap;
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u32 machwcap;
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@ -1643,11 +1643,15 @@ wlc_lcnphy_set_chanspec_tweaks(struct brcms_phy *pi, u16 chanspec)
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if (channel == 1 || channel == 2 || channel == 3 ||
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if (channel == 1 || channel == 2 || channel == 3 ||
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channel == 4 || channel == 9 ||
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channel == 4 || channel == 9 ||
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channel == 10 || channel == 11 || channel == 12) {
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channel == 10 || channel == 11 || channel == 12) {
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si_pmu_pllcontrol(pi->sh->sih, 0x2, 0xffffffff, 0x03000c04);
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bcma_chipco_pll_write(&pi->d11core->bus->drv_cc, 0x2,
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si_pmu_pllcontrol(pi->sh->sih, 0x3, 0xffffff, 0x0);
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0x03000c04);
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si_pmu_pllcontrol(pi->sh->sih, 0x4, 0xffffffff, 0x200005c0);
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bcma_chipco_pll_maskset(&pi->d11core->bus->drv_cc, 0x3,
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~0x00ffffff, 0x0);
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bcma_chipco_pll_write(&pi->d11core->bus->drv_cc, 0x4,
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0x200005c0);
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si_pmu_pllupd(pi->sh->sih);
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bcma_cc_set32(&pi->d11core->bus->drv_cc, BCMA_CC_PMU_CTL,
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BCMA_CC_PMU_CTL_PLL_UPD);
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write_phy_reg(pi, 0x942, 0);
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write_phy_reg(pi, 0x942, 0);
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wlc_lcnphy_txrx_spur_avoidance_mode(pi, false);
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wlc_lcnphy_txrx_spur_avoidance_mode(pi, false);
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pi_lcn->lcnphy_spurmod = false;
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pi_lcn->lcnphy_spurmod = false;
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@ -1655,11 +1659,15 @@ wlc_lcnphy_set_chanspec_tweaks(struct brcms_phy *pi, u16 chanspec)
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write_phy_reg(pi, 0x425, 0x5907);
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write_phy_reg(pi, 0x425, 0x5907);
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} else {
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} else {
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si_pmu_pllcontrol(pi->sh->sih, 0x2, 0xffffffff, 0x03140c04);
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bcma_chipco_pll_write(&pi->d11core->bus->drv_cc, 0x2,
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si_pmu_pllcontrol(pi->sh->sih, 0x3, 0xffffff, 0x333333);
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0x03140c04);
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si_pmu_pllcontrol(pi->sh->sih, 0x4, 0xffffffff, 0x202c2820);
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bcma_chipco_pll_maskset(&pi->d11core->bus->drv_cc, 0x3,
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~0x00ffffff, 0x333333);
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bcma_chipco_pll_write(&pi->d11core->bus->drv_cc, 0x4,
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0x202c2820);
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si_pmu_pllupd(pi->sh->sih);
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bcma_cc_set32(&pi->d11core->bus->drv_cc, BCMA_CC_PMU_CTL,
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BCMA_CC_PMU_CTL_PLL_UPD);
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write_phy_reg(pi, 0x942, 0);
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write_phy_reg(pi, 0x942, 0);
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wlc_lcnphy_txrx_spur_avoidance_mode(pi, true);
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wlc_lcnphy_txrx_spur_avoidance_mode(pi, true);
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@ -4864,9 +4872,10 @@ void wlc_phy_init_lcnphy(struct brcms_phy *pi)
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wlc_phy_chanspec_set((struct brcms_phy_pub *) pi, pi->radio_chanspec);
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wlc_phy_chanspec_set((struct brcms_phy_pub *) pi, pi->radio_chanspec);
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si_pmu_regcontrol(pi->sh->sih, 0, 0xf, 0x9);
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bcma_chipco_regctl_maskset(&pi->d11core->bus->drv_cc, 0, ~0xf, 0x9);
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si_pmu_chipcontrol(pi->sh->sih, 0, 0xffffffff, 0x03CDDDDD);
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bcma_chipco_chipctl_maskset(&pi->d11core->bus->drv_cc, 0, 0x0,
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0x03CDDDDD);
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if ((pi->sh->boardflags & BFL_FEM)
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if ((pi->sh->boardflags & BFL_FEM)
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&& wlc_lcnphy_tempsense_based_pwr_ctrl_enabled(pi))
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&& wlc_lcnphy_tempsense_based_pwr_ctrl_enabled(pi))
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@ -5078,7 +5087,7 @@ bool wlc_phy_attach_lcnphy(struct brcms_phy *pi)
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pi->hwpwrctrl_capable = true;
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pi->hwpwrctrl_capable = true;
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}
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}
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pi->xtalfreq = si_pmu_alp_clock(pi->sh->sih);
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pi->xtalfreq = bcma_chipco_get_alp_clock(&pi->d11core->bus->drv_cc);
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pi_lcn->lcnphy_papd_rxGnCtrl_init = 0;
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pi_lcn->lcnphy_papd_rxGnCtrl_init = 0;
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pi->pi_fptr.init = wlc_phy_init_lcnphy;
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pi->pi_fptr.init = wlc_phy_init_lcnphy;
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@ -19321,14 +19321,13 @@ void wlc_phy_init_nphy(struct brcms_phy *pi)
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(pi->sh->chippkg == BCMA_PKG_ID_BCM4718))) {
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(pi->sh->chippkg == BCMA_PKG_ID_BCM4718))) {
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if ((pi->sh->boardflags & BFL_EXTLNA) &&
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if ((pi->sh->boardflags & BFL_EXTLNA) &&
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(CHSPEC_IS2G(pi->radio_chanspec)))
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(CHSPEC_IS2G(pi->radio_chanspec)))
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ai_cc_reg(pi->sh->sih,
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bcma_cc_set32(&pi->d11core->bus->drv_cc,
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offsetof(struct chipcregs, chipcontrol),
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BCMA_CC_CHIPCTL, 0x40);
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0x40, 0x40);
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}
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}
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if ((!PHY_IPA(pi)) && (pi->sh->chip == BCMA_CHIP_ID_BCM5357))
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if ((!PHY_IPA(pi)) && (pi->sh->chip == BCMA_CHIP_ID_BCM5357))
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si_pmu_chipcontrol(pi->sh->sih, 1, CCTRL5357_EXTPA,
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bcma_chipco_chipctl_maskset(&pi->d11core->bus->drv_cc, 1,
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CCTRL5357_EXTPA);
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~CCTRL5357_EXTPA, CCTRL5357_EXTPA);
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if ((pi->nphy_gband_spurwar2_en) && CHSPEC_IS2G(pi->radio_chanspec) &&
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if ((pi->nphy_gband_spurwar2_en) && CHSPEC_IS2G(pi->radio_chanspec) &&
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CHSPEC_IS40(pi->radio_chanspec)) {
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CHSPEC_IS40(pi->radio_chanspec)) {
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@ -21133,7 +21132,6 @@ wlc_phy_chanspec_nphy_setup(struct brcms_phy *pi, u16 chanspec,
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const struct nphy_sfo_cfg *ci)
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const struct nphy_sfo_cfg *ci)
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{
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{
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u16 val;
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u16 val;
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struct si_info *sii = container_of(pi->sh->sih, struct si_info, pub);
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val = read_phy_reg(pi, 0x09) & NPHY_BandControl_currentBand;
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val = read_phy_reg(pi, 0x09) & NPHY_BandControl_currentBand;
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if (CHSPEC_IS5G(chanspec) && !val) {
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if (CHSPEC_IS5G(chanspec) && !val) {
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@ -21221,11 +21219,11 @@ wlc_phy_chanspec_nphy_setup(struct brcms_phy *pi, u16 chanspec,
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if ((pi->sh->chip == BCMA_CHIP_ID_BCM4716) ||
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if ((pi->sh->chip == BCMA_CHIP_ID_BCM4716) ||
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(pi->sh->chip == BCMA_CHIP_ID_BCM43225)) {
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(pi->sh->chip == BCMA_CHIP_ID_BCM43225)) {
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bcma_pmu_spuravoid_pllupdate(&sii->icbus->drv_cc,
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bcma_pmu_spuravoid_pllupdate(&pi->d11core->bus->drv_cc,
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spuravoid);
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spuravoid);
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} else {
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} else {
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wlapi_bmac_core_phypll_ctl(pi->sh->physhim, false);
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wlapi_bmac_core_phypll_ctl(pi->sh->physhim, false);
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bcma_pmu_spuravoid_pllupdate(&sii->icbus->drv_cc,
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bcma_pmu_spuravoid_pllupdate(&pi->d11core->bus->drv_cc,
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spuravoid);
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spuravoid);
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wlapi_bmac_core_phypll_ctl(pi->sh->physhim, true);
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wlapi_bmac_core_phypll_ctl(pi->sh->physhim, true);
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}
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}
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@ -115,60 +115,6 @@ u16 si_pmu_fast_pwrup_delay(struct si_pub *sih)
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return (u16) delay;
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return (u16) delay;
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}
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}
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/* Read/write a chipcontrol reg */
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u32 si_pmu_chipcontrol(struct si_pub *sih, uint reg, u32 mask, u32 val)
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{
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ai_cc_reg(sih, offsetof(struct chipcregs, chipcontrol_addr), ~0, reg);
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return ai_cc_reg(sih, offsetof(struct chipcregs, chipcontrol_data),
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mask, val);
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}
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/* Read/write a regcontrol reg */
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u32 si_pmu_regcontrol(struct si_pub *sih, uint reg, u32 mask, u32 val)
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{
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ai_cc_reg(sih, offsetof(struct chipcregs, regcontrol_addr), ~0, reg);
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return ai_cc_reg(sih, offsetof(struct chipcregs, regcontrol_data),
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mask, val);
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}
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/* Read/write a pllcontrol reg */
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u32 si_pmu_pllcontrol(struct si_pub *sih, uint reg, u32 mask, u32 val)
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{
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ai_cc_reg(sih, offsetof(struct chipcregs, pllcontrol_addr), ~0, reg);
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return ai_cc_reg(sih, offsetof(struct chipcregs, pllcontrol_data),
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mask, val);
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}
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/* PMU PLL update */
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void si_pmu_pllupd(struct si_pub *sih)
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{
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ai_cc_reg(sih, offsetof(struct chipcregs, pmucontrol),
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PCTL_PLL_PLLCTL_UPD, PCTL_PLL_PLLCTL_UPD);
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}
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/* query alp/xtal clock frequency */
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u32 si_pmu_alp_clock(struct si_pub *sih)
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{
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u32 clock = ALP_CLOCK;
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/* bail out with default */
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if (!(ai_get_cccaps(sih) & CC_CAP_PMU))
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return clock;
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switch (ai_get_chip_id(sih)) {
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case BCMA_CHIP_ID_BCM43224:
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case BCMA_CHIP_ID_BCM43225:
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case BCMA_CHIP_ID_BCM4313:
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/* always 20Mhz */
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clock = 20000 * 1000;
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break;
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default:
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break;
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}
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return clock;
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}
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u32 si_pmu_measure_alpclk(struct si_pub *sih)
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u32 si_pmu_measure_alpclk(struct si_pub *sih)
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{
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{
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struct si_info *sii = container_of(sih, struct si_info, pub);
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struct si_info *sii = container_of(sih, struct si_info, pub);
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@ -21,12 +21,6 @@
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#include "types.h"
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#include "types.h"
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extern u16 si_pmu_fast_pwrup_delay(struct si_pub *sih);
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extern u16 si_pmu_fast_pwrup_delay(struct si_pub *sih);
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extern void si_pmu_sprom_enable(struct si_pub *sih, bool enable);
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extern u32 si_pmu_chipcontrol(struct si_pub *sih, uint reg, u32 mask, u32 val);
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extern u32 si_pmu_regcontrol(struct si_pub *sih, uint reg, u32 mask, u32 val);
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extern u32 si_pmu_alp_clock(struct si_pub *sih);
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extern void si_pmu_pllupd(struct si_pub *sih);
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extern u32 si_pmu_pllcontrol(struct si_pub *sih, uint reg, u32 mask, u32 val);
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extern u32 si_pmu_measure_alpclk(struct si_pub *sih);
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extern u32 si_pmu_measure_alpclk(struct si_pub *sih);
|
||||||
|
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||||||
#endif /* _BRCM_PMU_H_ */
|
#endif /* _BRCM_PMU_H_ */
|
||||||
|
Loading…
Reference in New Issue
Block a user