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arm64: dts: rockchip: support the pmu node for rk3399

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This patch adds to enable the ARM Performance Monitor Units for rk3399.
ARM cores often have a PMU for counting cpu and cache events like cache
misses and hits.

This uses the new interrupt-partition mechanism to allow the two pmu
instances to use the per-cpu interrupt.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This commit is contained in:
Caesar Wang 2016-09-06 02:17:15 +08:00 committed by Heiko Stuebner
parent 210bbd38bb
commit 6840eb0d76
1 changed files with 20 additions and 0 deletions
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20
arch/arm64/boot/dts/rockchip/rk3399.dtsi
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@ -153,6 +153,16 @@
}; };
}; };
pmu_a53 {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
};
pmu_a72 {
compatible = "arm,cortex-a72-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
};
psci { psci {
compatible = "arm,psci-1.0"; compatible = "arm,psci-1.0";
method = "smc"; method = "smc";
@ -340,6 +350,16 @@
msi-controller; msi-controller;
reg = <0x0 0xfee20000 0x0 0x20000>; reg = <0x0 0xfee20000 0x0 0x20000>;
}; };
ppi-partitions {
ppi_cluster0: interrupt-partition-0 {
affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
};
ppi_cluster1: interrupt-partition-1 {
affinity = <&cpu_b0 &cpu_b1>;
};
};
}; };
saradc: saradc@ff100000 { saradc: saradc@ff100000 {