forked from Minki/linux
ARM: OMAP: Proper handling of DMA4_IRQSTATUS_L0
The register bits are reset by writing one. Remove the unneeded reads and fix writes to not clear too many bits. Signed-off-by: Timo Teras <timo.teras@solidboot.com> Signed-off-by: Juha Yrjola <juha.yrjola@solidboot.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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@ -557,7 +557,7 @@ int omap_request_dma(int dev_id, const char *dev_name,
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omap_enable_channel_irq(free_ch);
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/* Clear the CSR register and IRQ status register */
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OMAP_DMA_CSR_REG(free_ch) = OMAP2_DMA_CSR_CLEAR_MASK;
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omap_writel(~0x0, OMAP_DMA4_IRQSTATUS_L0);
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omap_writel(1 << free_ch, OMAP_DMA4_IRQSTATUS_L0);
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}
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*dma_ch_out = free_ch;
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@ -597,10 +597,7 @@ void omap_free_dma(int lch)
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/* Clear the CSR register and IRQ status register */
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OMAP_DMA_CSR_REG(lch) = OMAP2_DMA_CSR_CLEAR_MASK;
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val = omap_readl(OMAP_DMA4_IRQSTATUS_L0);
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val |= 1 << lch;
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omap_writel(val, OMAP_DMA4_IRQSTATUS_L0);
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omap_writel(1 << lch, OMAP_DMA4_IRQSTATUS_L0);
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/* Disable all DMA interrupts for the channel. */
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OMAP_DMA_CICR_REG(lch) = 0;
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@ -927,7 +924,6 @@ static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
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static int omap2_dma_handle_ch(int ch)
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{
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u32 status = OMAP_DMA_CSR_REG(ch);
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u32 val;
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if (!status)
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return 0;
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@ -948,11 +944,7 @@ static int omap2_dma_handle_ch(int ch)
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dma_chan[ch].dev_id);
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OMAP_DMA_CSR_REG(ch) = OMAP2_DMA_CSR_CLEAR_MASK;
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val = omap_readl(OMAP_DMA4_IRQSTATUS_L0);
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/* ch in this function is from 0-31 while in register it is 1-32 */
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val = 1 << (ch);
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omap_writel(val, OMAP_DMA4_IRQSTATUS_L0);
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omap_writel(1 << ch, OMAP_DMA4_IRQSTATUS_L0);
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if (likely(dma_chan[ch].callback != NULL))
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dma_chan[ch].callback(ch, status, dma_chan[ch].data);
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