forked from Minki/linux
net: phy: added the LAN937x phy support
LAN937x T1 switch is based on LAN87xx Phy, so reusing the init script of the LAN87xx. There is a workaround in accessing the DSP bank register for LAN937x Phy. Whenever there is a bank switch to DSP registers, then we need a one dummy read access before proceeding to the actual register access. Signed-off-by: Prasanna Vengateshan <prasanna.vengateshan@microchip.com> Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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8637034bc6
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680baca546
@ -8,13 +8,17 @@
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#include <linux/phy.h>
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#include <linux/phy.h>
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#include <linux/ethtool.h>
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#include <linux/ethtool.h>
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#include <linux/ethtool_netlink.h>
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#include <linux/ethtool_netlink.h>
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#include <linux/bitfield.h>
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#define PHY_ID_LAN87XX 0x0007c150
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#define PHY_ID_LAN87XX 0x0007c150
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#define PHY_ID_LAN937X 0x0007c180
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/* External Register Control Register */
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/* External Register Control Register */
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#define LAN87XX_EXT_REG_CTL (0x14)
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#define LAN87XX_EXT_REG_CTL (0x14)
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#define LAN87XX_EXT_REG_CTL_RD_CTL (0x1000)
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#define LAN87XX_EXT_REG_CTL_RD_CTL (0x1000)
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#define LAN87XX_EXT_REG_CTL_WR_CTL (0x0800)
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#define LAN87XX_EXT_REG_CTL_WR_CTL (0x0800)
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#define LAN87XX_REG_BANK_SEL_MASK GENMASK(10, 8)
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#define LAN87XX_REG_ADDR_MASK GENMASK(7, 0)
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/* External Register Read Data Register */
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/* External Register Read Data Register */
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#define LAN87XX_EXT_REG_RD_DATA (0x15)
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#define LAN87XX_EXT_REG_RD_DATA (0x15)
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@ -76,7 +80,7 @@
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#define T1_PST_EQ_LCK_STG1_FRZ_CFG 0x6E
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#define T1_PST_EQ_LCK_STG1_FRZ_CFG 0x6E
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#define DRIVER_AUTHOR "Nisar Sayed <nisar.sayed@microchip.com>"
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#define DRIVER_AUTHOR "Nisar Sayed <nisar.sayed@microchip.com>"
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#define DRIVER_DESC "Microchip LAN87XX T1 PHY driver"
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#define DRIVER_DESC "Microchip LAN87XX/LAN937x T1 PHY driver"
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struct access_ereg_val {
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struct access_ereg_val {
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u8 mode;
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u8 mode;
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@ -86,6 +90,37 @@ struct access_ereg_val {
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u16 mask;
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u16 mask;
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};
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};
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static int lan937x_dsp_workaround(struct phy_device *phydev, u16 ereg, u8 bank)
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{
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u8 prev_bank;
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int rc = 0;
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u16 val;
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mutex_lock(&phydev->lock);
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/* Read previous selected bank */
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rc = phy_read(phydev, LAN87XX_EXT_REG_CTL);
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if (rc < 0)
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goto out_unlock;
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/* store the prev_bank */
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prev_bank = FIELD_GET(LAN87XX_REG_BANK_SEL_MASK, rc);
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if (bank != prev_bank && bank == PHYACC_ATTR_BANK_DSP) {
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val = ereg & ~LAN87XX_REG_ADDR_MASK;
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val &= ~LAN87XX_EXT_REG_CTL_WR_CTL;
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val |= LAN87XX_EXT_REG_CTL_RD_CTL;
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/* access twice for DSP bank change,dummy access */
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rc = phy_write(phydev, LAN87XX_EXT_REG_CTL, val);
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}
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out_unlock:
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mutex_unlock(&phydev->lock);
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return rc;
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}
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static int access_ereg(struct phy_device *phydev, u8 mode, u8 bank,
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static int access_ereg(struct phy_device *phydev, u8 mode, u8 bank,
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u8 offset, u16 val)
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u8 offset, u16 val)
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{
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{
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@ -114,6 +149,13 @@ static int access_ereg(struct phy_device *phydev, u8 mode, u8 bank,
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ereg |= (bank << 8) | offset;
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ereg |= (bank << 8) | offset;
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/* DSP bank access workaround for lan937x */
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if (phydev->phy_id == PHY_ID_LAN937X) {
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rc = lan937x_dsp_workaround(phydev, ereg, bank);
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if (rc < 0)
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return rc;
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}
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rc = phy_write(phydev, LAN87XX_EXT_REG_CTL, ereg);
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rc = phy_write(phydev, LAN87XX_EXT_REG_CTL, ereg);
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if (rc < 0)
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if (rc < 0)
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return rc;
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return rc;
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@ -642,6 +684,16 @@ static struct phy_driver microchip_t1_phy_driver[] = {
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.resume = genphy_resume,
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.resume = genphy_resume,
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.cable_test_start = lan87xx_cable_test_start,
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.cable_test_start = lan87xx_cable_test_start,
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.cable_test_get_status = lan87xx_cable_test_get_status,
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.cable_test_get_status = lan87xx_cable_test_get_status,
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},
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{
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PHY_ID_MATCH_MODEL(PHY_ID_LAN937X),
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.name = "Microchip LAN937x T1",
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.features = PHY_BASIC_T1_FEATURES,
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.config_init = lan87xx_config_init,
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.suspend = genphy_suspend,
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.resume = genphy_resume,
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.cable_test_start = lan87xx_cable_test_start,
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.cable_test_get_status = lan87xx_cable_test_get_status,
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}
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}
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};
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};
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@ -649,6 +701,7 @@ module_phy_driver(microchip_t1_phy_driver);
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static struct mdio_device_id __maybe_unused microchip_t1_tbl[] = {
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static struct mdio_device_id __maybe_unused microchip_t1_tbl[] = {
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{ PHY_ID_MATCH_MODEL(PHY_ID_LAN87XX) },
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{ PHY_ID_MATCH_MODEL(PHY_ID_LAN87XX) },
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{ PHY_ID_MATCH_MODEL(PHY_ID_LAN937X) },
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{ }
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{ }
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};
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};
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