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mfd: rtsx: Fix checkpatch warning

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WARNING: Avoid CamelCase: <min_N>
+	u8 N, min_N, max_N, clk_divider;

WARNING: Avoid CamelCase: <max_N>
+	u8 N, min_N, max_N, clk_divider;

Signed-off-by: Wei WANG <wei_wang@realsil.com.cn>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
This commit is contained in:
Wei WANG 2013-01-29 15:21:35 +08:00 committed by Samuel Ortiz
parent f84ef04227
commit 678cacdfda
1 changed files with 13 additions and 13 deletions
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26
drivers/mfd/rtsx_pcr.c
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@ -590,7 +590,7 @@ int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk) u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk)
{ {
int err, clk; int err, clk;
u8 N, min_N, max_N, clk_divider; u8 n, min_n, max_n, clk_divider;
u8 mcu_cnt, div, max_div; u8 mcu_cnt, div, max_div;
u8 depth[] = { u8 depth[] = {
[RTSX_SSC_DEPTH_4M] = SSC_DEPTH_4M, [RTSX_SSC_DEPTH_4M] = SSC_DEPTH_4M,
@ -615,8 +615,8 @@ int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
card_clock /= 1000000; card_clock /= 1000000;
dev_dbg(&(pcr->pci->dev), "Switch card clock to %dMHz\n", card_clock); dev_dbg(&(pcr->pci->dev), "Switch card clock to %dMHz\n", card_clock);
min_N = 80; min_n = 80;
max_N = 208; max_n = 208;
max_div = CLK_DIV_8; max_div = CLK_DIV_8;
clk = card_clock; clk = card_clock;
@ -630,30 +630,30 @@ int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
return 0; return 0;
if (pcr->ops->conv_clk_and_div_n) if (pcr->ops->conv_clk_and_div_n)
N = (u8)pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N); n = (u8)pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N);
else else
N = (u8)(clk - 2); n = (u8)(clk - 2);
if ((clk <= 2) || (N > max_N)) if ((clk <= 2) || (n > max_n))
return -EINVAL; return -EINVAL;
mcu_cnt = (u8)(125/clk + 3); mcu_cnt = (u8)(125/clk + 3);
if (mcu_cnt > 15) if (mcu_cnt > 15)
mcu_cnt = 15; mcu_cnt = 15;
/* Make sure that the SSC clock div_n is equal or greater than min_N */ /* Make sure that the SSC clock div_n is equal or greater than min_n */
div = CLK_DIV_1; div = CLK_DIV_1;
while ((N < min_N) && (div < max_div)) { while ((n < min_n) && (div < max_div)) {
if (pcr->ops->conv_clk_and_div_n) { if (pcr->ops->conv_clk_and_div_n) {
int dbl_clk = pcr->ops->conv_clk_and_div_n(N, int dbl_clk = pcr->ops->conv_clk_and_div_n(n,
DIV_N_TO_CLK) * 2; DIV_N_TO_CLK) * 2;
N = (u8)pcr->ops->conv_clk_and_div_n(dbl_clk, n = (u8)pcr->ops->conv_clk_and_div_n(dbl_clk,
CLK_TO_DIV_N); CLK_TO_DIV_N);
} else { } else {
N = (N + 2) * 2 - 2; n = (n + 2) * 2 - 2;
} }
div++; div++;
} }
dev_dbg(&(pcr->pci->dev), "N = %d, div = %d\n", N, div); dev_dbg(&(pcr->pci->dev), "n = %d, div = %d\n", n, div);
ssc_depth = depth[ssc_depth]; ssc_depth = depth[ssc_depth];
if (double_clk) if (double_clk)
@ -670,7 +670,7 @@ int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0); rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);
rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2,
SSC_DEPTH_MASK, ssc_depth); SSC_DEPTH_MASK, ssc_depth);
rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, N); rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n);
rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB); rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB);
if (vpclk) { if (vpclk) {
rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,