forked from Minki/linux
PCI: tegra: Changes for v4.7-rc1
These patches update the Tegra PCIe host bridge controller device tree bindings and driver to cope with per-lane PHYs on Tegra124 and later. -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAABCAAGBQJXI3jqAAoJEN0jrNd/PrOhQ9AP/1PwtJFCkgK+BXNaNLxMjmcE PFNs4YFEbM7l/SJKXYKNiFMKN+M2pXe7jDxsefrKZd8Ad8qcNxPelzxZCzT0PYrX 4s4FXaztevBC+Kes0yvmBsu8k0ErGyu0XlE5rOTm6xgZp3BasKXv77ExeIIAmDyl eD+Ehgigb4pgN0Vp2sps+puWyndUtrCxlfZdg57MRCxYBYpeyacMjU6K/LptIYyF NJNhtPeJNX12LszblxM2agWBjRodzSr1qS4+ZtEBOxC/GRrpQ1XBdFNUI7LDF3B9 MXV1AiR7+NSSqPJSk6PMip87G9uYugvVofQQwls2YgP4f3VnEaDMSUexq5CTvA9S am48BsVQz2IHnkTA3YML0UQ/1pafD0W9ry3OyiVmu6RCnB5ROANoiX8+GoCS8yGB ptxb68rjVq+Y3bB17M1xWFmhFnO95aTYcS8QM7LUlsAdw17cmfhOfBKkTFUY/2j3 9hp0Zr+0I9Vtb1OFG3wwV6wtpVKTGn8QVgt7/XdzmY5Y9HnQaA4qK/T1OARvd+HL uLX/sh0KCC3pVavjjQZJBUYw4hoCgOWMz5NSP7CMJtIf+0VmAG4OxpvPWiuGqedB hLRqRuM3P5Rqb6AFXy6kmgJ3+mPLYbHxJ9NEbvVoovZMN5iepEHhhxbYvVc0hDXn D73a/QG/H7RczJeQbM0X =38Xd -----END PGP SIGNATURE----- Merge tag 'tegra-for-4.7-pci' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/drivers Merge "PCI: tegra: Changes for v4.7-rc1" from Thierry Reding: These patches update the Tegra PCIe host bridge controller device tree bindings and driver to cope with per-lane PHYs on Tegra124 and later. * tag 'tegra-for-4.7-pci' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: PCI: tegra: Support per-lane PHYs dt-bindings: pci: tegra: Update for per-lane PHYs
This commit is contained in:
Arnd Bergmann
commit
675de1d514
@ -60,11 +60,14 @@ Required properties:
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- afi
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- pcie_x
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Required properties on Tegra124 and later:
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Required properties on Tegra124 and later (deprecated):
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- phys: Must contain an entry for each entry in phy-names.
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- phy-names: Must include the following entries:
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- pcie
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These properties are deprecated in favour of per-lane PHYs define in each of
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the root ports (see below).
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Power supplies for Tegra20:
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- avdd-pex-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
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- vdd-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
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@ -122,11 +125,22 @@ Required properties:
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- Root port 0 uses 4 lanes, root port 1 is unused.
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- Both root ports use 2 lanes.
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Example:
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Required properties for Tegra124 and later:
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- phys: Must contain an phandle to a PHY for each entry in phy-names.
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- phy-names: Must include an entry for each active lane. Note that the number
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of entries does not have to (though usually will) be equal to the specified
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number of lanes in the nvidia,num-lanes property. Entries are of the form
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"pcie-N": where N ranges from 0 to the value specified in nvidia,num-lanes.
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Examples:
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=========
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Tegra20:
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--------
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SoC DTSI:
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pcie-controller {
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pcie-controller@80003000 {
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compatible = "nvidia,tegra20-pcie";
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device_type = "pci";
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reg = <0x80003000 0x00000800 /* PADS registers */
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@ -186,10 +200,9 @@ SoC DTSI:
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};
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};
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Board DTS:
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pcie-controller {
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pcie-controller@80003000 {
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status = "okay";
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vdd-supply = <&pci_vdd_reg>;
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@ -222,3 +235,204 @@ if a device on the PCI bus provides a non-probeable bus such as I2C or SPI,
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device nodes need to be added in order to allow the bus' children to be
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instantiated at the proper location in the operating system's device tree (as
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illustrated by the optional nodes in the example above).
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Tegra30:
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--------
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SoC DTSI:
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pcie-controller@00003000 {
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compatible = "nvidia,tegra30-pcie";
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device_type = "pci";
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reg = <0x00003000 0x00000800 /* PADS registers */
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0x00003800 0x00000200 /* AFI registers */
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0x10000000 0x10000000>; /* configuration space */
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reg-names = "pads", "afi", "cs";
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interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */
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GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
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interrupt-names = "intr", "msi";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
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bus-range = <0x00 0xff>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */
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0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */
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0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */
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0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */
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0x82000000 0 0x20000000 0x20000000 0 0x08000000 /* non-prefetchable memory */
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0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */
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clocks = <&tegra_car TEGRA30_CLK_PCIE>,
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<&tegra_car TEGRA30_CLK_AFI>,
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<&tegra_car TEGRA30_CLK_PLL_E>,
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<&tegra_car TEGRA30_CLK_CML0>;
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clock-names = "pex", "afi", "pll_e", "cml";
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resets = <&tegra_car 70>,
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<&tegra_car 72>,
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<&tegra_car 74>;
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reset-names = "pex", "afi", "pcie_x";
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status = "disabled";
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pci@1,0 {
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device_type = "pci";
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assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
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reg = <0x000800 0 0 0 0>;
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status = "disabled";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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nvidia,num-lanes = <2>;
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};
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pci@2,0 {
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device_type = "pci";
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assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
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reg = <0x001000 0 0 0 0>;
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status = "disabled";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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nvidia,num-lanes = <2>;
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};
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pci@3,0 {
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device_type = "pci";
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assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
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reg = <0x001800 0 0 0 0>;
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status = "disabled";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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nvidia,num-lanes = <2>;
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};
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};
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Board DTS:
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pcie-controller@00003000 {
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status = "okay";
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avdd-pexa-supply = <&ldo1_reg>;
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vdd-pexa-supply = <&ldo1_reg>;
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avdd-pexb-supply = <&ldo1_reg>;
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vdd-pexb-supply = <&ldo1_reg>;
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avdd-pex-pll-supply = <&ldo1_reg>;
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avdd-plle-supply = <&ldo1_reg>;
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vddio-pex-ctl-supply = <&sys_3v3_reg>;
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hvdd-pex-supply = <&sys_3v3_pexs_reg>;
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pci@1,0 {
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status = "okay";
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};
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pci@3,0 {
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status = "okay";
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};
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};
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Tegra124:
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---------
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SoC DTSI:
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pcie-controller@01003000 {
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compatible = "nvidia,tegra124-pcie";
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device_type = "pci";
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reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
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0x0 0x01003800 0x0 0x00000800 /* AFI registers */
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0x0 0x02000000 0x0 0x10000000>; /* configuration space */
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reg-names = "pads", "afi", "cs";
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interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
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<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
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interrupt-names = "intr", "msi";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
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bus-range = <0x00 0xff>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */
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0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */
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0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
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0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
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0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
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clocks = <&tegra_car TEGRA124_CLK_PCIE>,
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<&tegra_car TEGRA124_CLK_AFI>,
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<&tegra_car TEGRA124_CLK_PLL_E>,
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<&tegra_car TEGRA124_CLK_CML0>;
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clock-names = "pex", "afi", "pll_e", "cml";
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resets = <&tegra_car 70>,
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<&tegra_car 72>,
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<&tegra_car 74>;
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reset-names = "pex", "afi", "pcie_x";
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status = "disabled";
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pci@1,0 {
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device_type = "pci";
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assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
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reg = <0x000800 0 0 0 0>;
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status = "disabled";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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nvidia,num-lanes = <2>;
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};
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pci@2,0 {
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device_type = "pci";
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assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
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reg = <0x001000 0 0 0 0>;
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status = "disabled";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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nvidia,num-lanes = <1>;
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};
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};
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Board DTS:
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pcie-controller@01003000 {
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status = "okay";
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avddio-pex-supply = <&vdd_1v05_run>;
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dvddio-pex-supply = <&vdd_1v05_run>;
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avdd-pex-pll-supply = <&vdd_1v05_run>;
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hvdd-pex-supply = <&vdd_3v3_lp0>;
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hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>;
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vddio-pex-ctl-supply = <&vdd_3v3_lp0>;
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avdd-pll-erefe-supply = <&avdd_1v05_run>;
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/* Mini PCIe */
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pci@1,0 {
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phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>;
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phy-names = "pcie-0";
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status = "okay";
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};
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/* Gigabit Ethernet */
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pci@2,0 {
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phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>;
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phy-names = "pcie-0";
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status = "okay";
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};
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};
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@ -295,6 +295,7 @@ struct tegra_pcie {
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struct reset_control *afi_rst;
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struct reset_control *pcie_xrst;
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bool legacy_phy;
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struct phy *phy;
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struct tegra_msi msi;
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@ -311,11 +312,14 @@ struct tegra_pcie {
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struct tegra_pcie_port {
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struct tegra_pcie *pcie;
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struct device_node *np;
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struct list_head list;
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struct resource regs;
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void __iomem *base;
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unsigned int index;
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unsigned int lanes;
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struct phy **phys;
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};
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struct tegra_pcie_bus {
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@ -860,6 +864,128 @@ static int tegra_pcie_phy_enable(struct tegra_pcie *pcie)
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return 0;
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}
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static int tegra_pcie_phy_disable(struct tegra_pcie *pcie)
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{
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const struct tegra_pcie_soc_data *soc = pcie->soc_data;
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u32 value;
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/* disable TX/RX data */
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value = pads_readl(pcie, PADS_CTL);
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value &= ~(PADS_CTL_TX_DATA_EN_1L | PADS_CTL_RX_DATA_EN_1L);
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pads_writel(pcie, value, PADS_CTL);
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/* override IDDQ */
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value = pads_readl(pcie, PADS_CTL);
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value |= PADS_CTL_IDDQ_1L;
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pads_writel(pcie, PADS_CTL, value);
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/* reset PLL */
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value = pads_readl(pcie, soc->pads_pll_ctl);
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value &= ~PADS_PLL_CTL_RST_B4SM;
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pads_writel(pcie, value, soc->pads_pll_ctl);
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usleep_range(20, 100);
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return 0;
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}
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static int tegra_pcie_port_phy_power_on(struct tegra_pcie_port *port)
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{
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struct device *dev = port->pcie->dev;
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unsigned int i;
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int err;
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for (i = 0; i < port->lanes; i++) {
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err = phy_power_on(port->phys[i]);
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if (err < 0) {
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dev_err(dev, "failed to power on PHY#%u: %d\n", i,
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err);
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return err;
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}
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}
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return 0;
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}
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static int tegra_pcie_port_phy_power_off(struct tegra_pcie_port *port)
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{
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struct device *dev = port->pcie->dev;
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unsigned int i;
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int err;
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for (i = 0; i < port->lanes; i++) {
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err = phy_power_off(port->phys[i]);
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if (err < 0) {
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dev_err(dev, "failed to power off PHY#%u: %d\n", i,
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err);
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return err;
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}
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}
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return 0;
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}
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static int tegra_pcie_phy_power_on(struct tegra_pcie *pcie)
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{
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struct tegra_pcie_port *port;
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int err;
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if (pcie->legacy_phy) {
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if (pcie->phy)
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err = phy_power_on(pcie->phy);
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else
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err = tegra_pcie_phy_enable(pcie);
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if (err < 0)
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dev_err(pcie->dev, "failed to power on PHY: %d\n", err);
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return err;
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}
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list_for_each_entry(port, &pcie->ports, list) {
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err = tegra_pcie_port_phy_power_on(port);
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if (err < 0) {
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dev_err(pcie->dev,
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"failed to power on PCIe port %u PHY: %d\n",
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port->index, err);
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return err;
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}
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}
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return 0;
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}
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static int tegra_pcie_phy_power_off(struct tegra_pcie *pcie)
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{
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struct tegra_pcie_port *port;
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int err;
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if (pcie->legacy_phy) {
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if (pcie->phy)
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err = phy_power_off(pcie->phy);
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else
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err = tegra_pcie_phy_disable(pcie);
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if (err < 0)
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dev_err(pcie->dev, "failed to power off PHY: %d\n",
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err);
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return err;
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}
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list_for_each_entry(port, &pcie->ports, list) {
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err = tegra_pcie_port_phy_power_off(port);
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if (err < 0) {
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dev_err(pcie->dev,
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"failed to power off PCIe port %u PHY: %d\n",
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port->index, err);
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return err;
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}
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}
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return 0;
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}
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static int tegra_pcie_enable_controller(struct tegra_pcie *pcie)
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{
|
||||
const struct tegra_pcie_soc_data *soc = pcie->soc_data;
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||||
@ -899,13 +1025,9 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie)
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afi_writel(pcie, value, AFI_FUSE);
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}
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|
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if (!pcie->phy)
|
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err = tegra_pcie_phy_enable(pcie);
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else
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err = phy_power_on(pcie->phy);
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|
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err = tegra_pcie_phy_power_on(pcie);
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if (err < 0) {
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dev_err(pcie->dev, "failed to power on PHY: %d\n", err);
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dev_err(pcie->dev, "failed to power on PHY(s): %d\n", err);
|
||||
return err;
|
||||
}
|
||||
|
||||
@ -942,9 +1064,9 @@ static void tegra_pcie_power_off(struct tegra_pcie *pcie)
|
||||
|
||||
/* TODO: disable and unprepare clocks? */
|
||||
|
||||
err = phy_power_off(pcie->phy);
|
||||
err = tegra_pcie_phy_power_off(pcie);
|
||||
if (err < 0)
|
||||
dev_warn(pcie->dev, "failed to power off PHY: %d\n", err);
|
||||
dev_err(pcie->dev, "failed to power off PHY(s): %d\n", err);
|
||||
|
||||
reset_control_assert(pcie->pcie_xrst);
|
||||
reset_control_assert(pcie->afi_rst);
|
||||
@ -1049,6 +1171,100 @@ static int tegra_pcie_resets_get(struct tegra_pcie *pcie)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tegra_pcie_phys_get_legacy(struct tegra_pcie *pcie)
|
||||
{
|
||||
int err;
|
||||
|
||||
pcie->phy = devm_phy_optional_get(pcie->dev, "pcie");
|
||||
if (IS_ERR(pcie->phy)) {
|
||||
err = PTR_ERR(pcie->phy);
|
||||
dev_err(pcie->dev, "failed to get PHY: %d\n", err);
|
||||
return err;
|
||||
}
|
||||
|
||||
err = phy_init(pcie->phy);
|
||||
if (err < 0) {
|
||||
dev_err(pcie->dev, "failed to initialize PHY: %d\n", err);
|
||||
return err;
|
||||
}
|
||||
|
||||
pcie->legacy_phy = true;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct phy *devm_of_phy_optional_get_index(struct device *dev,
|
||||
struct device_node *np,
|
||||
const char *consumer,
|
||||
unsigned int index)
|
||||
{
|
||||
struct phy *phy;
|
||||
char *name;
|
||||
|
||||
name = kasprintf(GFP_KERNEL, "%s-%u", consumer, index);
|
||||
if (!name)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
phy = devm_of_phy_get(dev, np, name);
|
||||
kfree(name);
|
||||
|
||||
if (IS_ERR(phy) && PTR_ERR(phy) == -ENODEV)
|
||||
phy = NULL;
|
||||
|
||||
return phy;
|
||||
}
|
||||
|
||||
static int tegra_pcie_port_get_phys(struct tegra_pcie_port *port)
|
||||
{
|
||||
struct device *dev = port->pcie->dev;
|
||||
struct phy *phy;
|
||||
unsigned int i;
|
||||
int err;
|
||||
|
||||
port->phys = devm_kcalloc(dev, sizeof(phy), port->lanes, GFP_KERNEL);
|
||||
if (!port->phys)
|
||||
return -ENOMEM;
|
||||
|
||||
for (i = 0; i < port->lanes; i++) {
|
||||
phy = devm_of_phy_optional_get_index(dev, port->np, "pcie", i);
|
||||
if (IS_ERR(phy)) {
|
||||
dev_err(dev, "failed to get PHY#%u: %ld\n", i,
|
||||
PTR_ERR(phy));
|
||||
return PTR_ERR(phy);
|
||||
}
|
||||
|
||||
err = phy_init(phy);
|
||||
if (err < 0) {
|
||||
dev_err(dev, "failed to initialize PHY#%u: %d\n", i,
|
||||
err);
|
||||
return err;
|
||||
}
|
||||
|
||||
port->phys[i] = phy;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tegra_pcie_phys_get(struct tegra_pcie *pcie)
|
||||
{
|
||||
const struct tegra_pcie_soc_data *soc = pcie->soc_data;
|
||||
struct device_node *np = pcie->dev->of_node;
|
||||
struct tegra_pcie_port *port;
|
||||
int err;
|
||||
|
||||
if (!soc->has_gen2 || of_find_property(np, "phys", NULL) != NULL)
|
||||
return tegra_pcie_phys_get_legacy(pcie);
|
||||
|
||||
list_for_each_entry(port, &pcie->ports, list) {
|
||||
err = tegra_pcie_port_get_phys(port);
|
||||
if (err < 0)
|
||||
return err;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tegra_pcie_get_resources(struct tegra_pcie *pcie)
|
||||
{
|
||||
struct platform_device *pdev = to_platform_device(pcie->dev);
|
||||
@ -1067,16 +1283,9 @@ static int tegra_pcie_get_resources(struct tegra_pcie *pcie)
|
||||
return err;
|
||||
}
|
||||
|
||||
pcie->phy = devm_phy_optional_get(pcie->dev, "pcie");
|
||||
if (IS_ERR(pcie->phy)) {
|
||||
err = PTR_ERR(pcie->phy);
|
||||
dev_err(&pdev->dev, "failed to get PHY: %d\n", err);
|
||||
return err;
|
||||
}
|
||||
|
||||
err = phy_init(pcie->phy);
|
||||
err = tegra_pcie_phys_get(pcie);
|
||||
if (err < 0) {
|
||||
dev_err(&pdev->dev, "failed to initialize PHY: %d\n", err);
|
||||
dev_err(&pdev->dev, "failed to get PHYs: %d\n", err);
|
||||
return err;
|
||||
}
|
||||
|
||||
@ -1752,6 +1961,7 @@ static int tegra_pcie_parse_dt(struct tegra_pcie *pcie)
|
||||
rp->index = index;
|
||||
rp->lanes = value;
|
||||
rp->pcie = pcie;
|
||||
rp->np = port;
|
||||
|
||||
rp->base = devm_ioremap_resource(pcie->dev, &rp->regs);
|
||||
if (IS_ERR(rp->base))
|
||||
|
||||
Loading…
Reference in New Issue
Block a user