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clk: bcm2835: pll_off should only update CM_PLL_ANARST

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bcm2835_pll_off is currently assigning CM_PLL_ANARST to the control
register, which may lose the other bits that are currently set by the
clock dividers.

It also now locks during the read/modify/write cycle of both
registers.

Fixes: 41691b8862 ("clk: bcm2835: Add support for programming the
audio domain clocks")

Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Anholt <eric@anholt.net>
This commit is contained in:
Martin Sperl 2016-02-29 11:39:17 +00:00 committed by Eric Anholt
parent 4d3ac66624
commit 6727f086cf
1 changed files with 8 additions and 2 deletions
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10
drivers/clk/bcm/clk-bcm2835.c
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@ -910,8 +910,14 @@ static void bcm2835_pll_off(struct clk_hw *hw)
struct bcm2835_cprman *cprman = pll->cprman; struct bcm2835_cprman *cprman = pll->cprman;
const struct bcm2835_pll_data *data = pll->data; const struct bcm2835_pll_data *data = pll->data;
cprman_write(cprman, data->cm_ctrl_reg, CM_PLL_ANARST); spin_lock(&cprman->regs_lock);
cprman_write(cprman, data->a2w_ctrl_reg, A2W_PLL_CTRL_PWRDN); cprman_write(cprman, data->cm_ctrl_reg,
cprman_read(cprman, data->cm_ctrl_reg) |
CM_PLL_ANARST);
cprman_write(cprman, data->a2w_ctrl_reg,
cprman_read(cprman, data->a2w_ctrl_reg) |
A2W_PLL_CTRL_PWRDN);
spin_unlock(&cprman->regs_lock);
} }
static int bcm2835_pll_on(struct clk_hw *hw) static int bcm2835_pll_on(struct clk_hw *hw)