ARM: dts: rockchip: add phandles to secondary cpu cores
Add phandles to secondary cpu cores as we may need to reference these down the road as well. Signed-off-by: Heiko Stuebner <heiko.stuebner@bq.com>
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0222aac448
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66dc478a28
@ -28,7 +28,7 @@
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operating-points-v2 = <&cpu0_opp_table>;
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operating-points-v2 = <&cpu0_opp_table>;
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resets = <&cru SRST_CORE0>;
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resets = <&cru SRST_CORE0>;
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};
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};
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cpu@1 {
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cpu1: cpu@1 {
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device_type = "cpu";
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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compatible = "arm,cortex-a9";
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next-level-cache = <&L2>;
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next-level-cache = <&L2>;
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@ -36,7 +36,7 @@
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operating-points-v2 = <&cpu0_opp_table>;
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operating-points-v2 = <&cpu0_opp_table>;
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resets = <&cru SRST_CORE1>;
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resets = <&cru SRST_CORE1>;
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};
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};
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cpu@2 {
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cpu2: cpu@2 {
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device_type = "cpu";
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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compatible = "arm,cortex-a9";
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next-level-cache = <&L2>;
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next-level-cache = <&L2>;
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@ -44,7 +44,7 @@
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operating-points-v2 = <&cpu0_opp_table>;
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operating-points-v2 = <&cpu0_opp_table>;
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resets = <&cru SRST_CORE2>;
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resets = <&cru SRST_CORE2>;
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};
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};
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cpu@3 {
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cpu3: cpu@3 {
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device_type = "cpu";
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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compatible = "arm,cortex-a9";
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next-level-cache = <&L2>;
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next-level-cache = <&L2>;
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