forked from Minki/linux
clk: renesas: r9a07g044: Add P2 Clock support
Add support for P2 clock which is sourced from pll3_div2_4_2. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20210626081344.5783-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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@ -31,6 +31,7 @@ enum clk_ids {
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CLK_PLL3,
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CLK_PLL3_DIV2,
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CLK_PLL3_DIV2_4,
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CLK_PLL3_DIV2_4_2,
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CLK_PLL3_DIV4,
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CLK_PLL4,
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CLK_PLL5,
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@ -68,6 +69,7 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {
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DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2),
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DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4),
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DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2),
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DEF_FIXED(".pll3_div4", CLK_PLL3_DIV4, CLK_PLL3, 1, 4),
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/* Core output clk */
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@ -77,6 +79,8 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {
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DEF_FIXED("TSU", R9A07G044_CLK_TSU, CLK_PLL2_DIV20, 1, 1),
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DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV2_4,
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DIVPL3B, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
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DEF_DIV("P2", R9A07G044_CLK_P2, CLK_PLL3_DIV2_4_2,
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DIVPL3A, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
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};
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static struct rzg2l_mod_clk r9a07g044_mod_clks[] = {
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@ -21,6 +21,7 @@
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#define DDIV_PACK(offset, bitpos, size) \
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(((offset) << 20) | ((bitpos) << 12) | ((size) << 8))
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#define DIVPL2A DDIV_PACK(CPG_PL2_DDIV, 0, 3)
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#define DIVPL3A DDIV_PACK(CPG_PL3A_DDIV, 0, 3)
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#define DIVPL3B DDIV_PACK(CPG_PL3A_DDIV, 4, 3)
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/**
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