net/mlx5: Manage ICM of type modify-header pattern
Added support for managing new type of ICM for devices that support sw_owner_v2. Signed-off-by: Erez Shitrit <erezsh@mellanox.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Signed-off-by: Leon Romanovsky <leonro@nvidia.com> Acked-by: Saeed Mahameed <saeedm@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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795e10b450
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667658364b
@ -12,13 +12,16 @@ struct mlx5_dm {
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spinlock_t lock;
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spinlock_t lock;
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unsigned long *steering_sw_icm_alloc_blocks;
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unsigned long *steering_sw_icm_alloc_blocks;
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unsigned long *header_modify_sw_icm_alloc_blocks;
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unsigned long *header_modify_sw_icm_alloc_blocks;
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unsigned long *header_modify_pattern_sw_icm_alloc_blocks;
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};
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};
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struct mlx5_dm *mlx5_dm_create(struct mlx5_core_dev *dev)
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struct mlx5_dm *mlx5_dm_create(struct mlx5_core_dev *dev)
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{
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{
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u64 header_modify_pattern_icm_blocks = 0;
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u64 header_modify_icm_blocks = 0;
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u64 header_modify_icm_blocks = 0;
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u64 steering_icm_blocks = 0;
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u64 steering_icm_blocks = 0;
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struct mlx5_dm *dm;
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struct mlx5_dm *dm;
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bool support_v2;
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if (!(MLX5_CAP_GEN_64(dev, general_obj_types) & MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM))
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if (!(MLX5_CAP_GEN_64(dev, general_obj_types) & MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM))
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return NULL;
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return NULL;
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@ -53,8 +56,27 @@ struct mlx5_dm *mlx5_dm_create(struct mlx5_core_dev *dev)
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goto err_modify_hdr;
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goto err_modify_hdr;
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}
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}
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support_v2 = MLX5_CAP_FLOWTABLE_NIC_RX(dev, sw_owner_v2) &&
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MLX5_CAP_FLOWTABLE_NIC_TX(dev, sw_owner_v2) &&
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MLX5_CAP64_DEV_MEM(dev, header_modify_pattern_sw_icm_start_address);
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if (support_v2) {
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header_modify_pattern_icm_blocks =
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BIT(MLX5_CAP_DEV_MEM(dev, log_header_modify_pattern_sw_icm_size) -
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MLX5_LOG_SW_ICM_BLOCK_SIZE(dev));
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dm->header_modify_pattern_sw_icm_alloc_blocks =
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kcalloc(BITS_TO_LONGS(header_modify_pattern_icm_blocks),
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sizeof(unsigned long), GFP_KERNEL);
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if (!dm->header_modify_pattern_sw_icm_alloc_blocks)
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goto err_pattern;
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}
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return dm;
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return dm;
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err_pattern:
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kfree(dm->header_modify_sw_icm_alloc_blocks);
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err_modify_hdr:
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err_modify_hdr:
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kfree(dm->steering_sw_icm_alloc_blocks);
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kfree(dm->steering_sw_icm_alloc_blocks);
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@ -86,6 +108,14 @@ void mlx5_dm_cleanup(struct mlx5_core_dev *dev)
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kfree(dm->header_modify_sw_icm_alloc_blocks);
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kfree(dm->header_modify_sw_icm_alloc_blocks);
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}
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}
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if (dm->header_modify_pattern_sw_icm_alloc_blocks) {
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WARN_ON(!bitmap_empty(dm->header_modify_pattern_sw_icm_alloc_blocks,
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BIT(MLX5_CAP_DEV_MEM(dev,
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log_header_modify_pattern_sw_icm_size) -
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MLX5_LOG_SW_ICM_BLOCK_SIZE(dev))));
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kfree(dm->header_modify_pattern_sw_icm_alloc_blocks);
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}
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kfree(dm);
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kfree(dm);
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}
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}
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@ -130,6 +160,13 @@ int mlx5_dm_sw_icm_alloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
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log_header_modify_sw_icm_size);
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log_header_modify_sw_icm_size);
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block_map = dm->header_modify_sw_icm_alloc_blocks;
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block_map = dm->header_modify_sw_icm_alloc_blocks;
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break;
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break;
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case MLX5_SW_ICM_TYPE_HEADER_MODIFY_PATTERN:
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icm_start_addr = MLX5_CAP64_DEV_MEM(dev,
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header_modify_pattern_sw_icm_start_address);
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log_icm_size = MLX5_CAP_DEV_MEM(dev,
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log_header_modify_pattern_sw_icm_size);
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block_map = dm->header_modify_pattern_sw_icm_alloc_blocks;
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break;
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default:
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default:
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return -EINVAL;
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return -EINVAL;
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}
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}
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@ -203,6 +240,11 @@ int mlx5_dm_sw_icm_dealloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type
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icm_start_addr = MLX5_CAP64_DEV_MEM(dev, header_modify_sw_icm_start_address);
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icm_start_addr = MLX5_CAP64_DEV_MEM(dev, header_modify_sw_icm_start_address);
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block_map = dm->header_modify_sw_icm_alloc_blocks;
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block_map = dm->header_modify_sw_icm_alloc_blocks;
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break;
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break;
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case MLX5_SW_ICM_TYPE_HEADER_MODIFY_PATTERN:
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icm_start_addr = MLX5_CAP64_DEV_MEM(dev,
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header_modify_pattern_sw_icm_start_address);
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block_map = dm->header_modify_pattern_sw_icm_alloc_blocks;
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break;
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default:
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default:
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return -EINVAL;
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return -EINVAL;
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}
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}
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@ -676,6 +676,7 @@ struct mlx5e_resources {
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enum mlx5_sw_icm_type {
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enum mlx5_sw_icm_type {
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MLX5_SW_ICM_TYPE_STEERING,
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MLX5_SW_ICM_TYPE_STEERING,
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MLX5_SW_ICM_TYPE_HEADER_MODIFY,
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MLX5_SW_ICM_TYPE_HEADER_MODIFY,
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MLX5_SW_ICM_TYPE_HEADER_MODIFY_PATTERN,
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};
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};
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#define MLX5_MAX_RESERVED_GIDS 8
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#define MLX5_MAX_RESERVED_GIDS 8
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