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arm64: dts: renesas: r8a774a1: Add SDHI nodes

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Add SDHI nodes to the DT of the r8a774a1 SoC.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Fabrizio Castro 2018-08-23 14:43:00 +01:00 committed by Simon Horman
parent 53ae5809d3
commit 663386c3e1
1 changed files with 48 additions and 0 deletions
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48
arch/arm64/boot/dts/renesas/r8a774a1.dtsi
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@ -627,6 +627,54 @@
status = "disabled"; status = "disabled";
}; };
sdhi0: sd@ee100000 {
compatible = "renesas,sdhi-r8a774a1",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee100000 0 0x2000>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 314>;
max-frequency = <200000000>;
power-domains = <&sysc 32>;
resets = <&cpg 314>;
status = "disabled";
};
sdhi1: sd@ee120000 {
compatible = "renesas,sdhi-r8a774a1",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee120000 0 0x2000>;
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 313>;
max-frequency = <200000000>;
power-domains = <&sysc 32>;
resets = <&cpg 313>;
status = "disabled";
};
sdhi2: sd@ee140000 {
compatible = "renesas,sdhi-r8a774a1",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee140000 0 0x2000>;
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 312>;
max-frequency = <200000000>;
power-domains = <&sysc 32>;
resets = <&cpg 312>;
status = "disabled";
};
sdhi3: sd@ee160000 {
compatible = "renesas,sdhi-r8a774a1",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee160000 0 0x2000>;
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 311>;
max-frequency = <200000000>;
power-domains = <&sysc 32>;
resets = <&cpg 311>;
status = "disabled";
};
gic: interrupt-controller@f1010000 { gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400"; compatible = "arm,gic-400";
#interrupt-cells = <3>; #interrupt-cells = <3>;