forked from Minki/linux
Merge branch 'bnxt_en-Add-support-for-new-57500-chips'
Michael Chan says: ==================== bnxt_en: Add support for new 57500 chips. This patch-set is larger than normal because I wanted a complete series to add basic support for the new 57500 chips. The new chips have the following main differences compared to legacy chips: 1. Requires the PF driver to allocate DMA context memory as a backing store. 2. New NQ (notification queue) for interrupt events. 3. One or more CP rings can be associated with an NQ. 4. 64-bit doorbells. Most other structures and firmware APIs are compatible with legacy devices with some exceptions. For example, ring groups are no longer used and RSS table format has changed. The patch-set includes the usual firmware spec. update, some refactoring and restructuring, and adding the new code to add basic support for the new class of devices. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
commit
65f2247d61
File diff suppressed because it is too large
Load Diff
@ -12,11 +12,11 @@
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#define BNXT_H
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#define DRV_MODULE_NAME "bnxt_en"
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#define DRV_MODULE_VERSION "1.9.2"
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#define DRV_MODULE_VERSION "1.10.0"
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#define DRV_VER_MAJ 1
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#define DRV_VER_MIN 9
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#define DRV_VER_UPD 2
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#define DRV_VER_MIN 10
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#define DRV_VER_UPD 0
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#include <linux/interrupt.h>
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#include <linux/rhashtable.h>
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@ -403,6 +403,19 @@ struct rx_tpa_end_cmp_ext {
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((rx_tpa_end_ext)->rx_tpa_end_cmp_errors_v2 & \
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cpu_to_le32(RX_TPA_END_CMP_ERRORS))
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struct nqe_cn {
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__le16 type;
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#define NQ_CN_TYPE_MASK 0x3fUL
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#define NQ_CN_TYPE_SFT 0
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#define NQ_CN_TYPE_CQ_NOTIFICATION 0x30UL
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#define NQ_CN_TYPE_LAST NQ_CN_TYPE_CQ_NOTIFICATION
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__le16 reserved16;
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__le32 cq_handle_low;
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__le32 v;
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#define NQ_CN_V 0x1UL
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__le32 cq_handle_high;
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};
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#define DB_IDX_MASK 0xffffff
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#define DB_IDX_VALID (0x1 << 26)
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#define DB_IRQ_DIS (0x1 << 27)
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@ -416,6 +429,25 @@ struct rx_tpa_end_cmp_ext {
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#define BNXT_MIN_ROCE_CP_RINGS 2
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#define BNXT_MIN_ROCE_STAT_CTXS 1
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/* 64-bit doorbell */
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#define DBR_INDEX_MASK 0x0000000000ffffffULL
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#define DBR_XID_MASK 0x000fffff00000000ULL
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#define DBR_XID_SFT 32
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#define DBR_PATH_L2 (0x1ULL << 56)
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#define DBR_TYPE_SQ (0x0ULL << 60)
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#define DBR_TYPE_RQ (0x1ULL << 60)
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#define DBR_TYPE_SRQ (0x2ULL << 60)
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#define DBR_TYPE_SRQ_ARM (0x3ULL << 60)
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#define DBR_TYPE_CQ (0x4ULL << 60)
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#define DBR_TYPE_CQ_ARMSE (0x5ULL << 60)
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#define DBR_TYPE_CQ_ARMALL (0x6ULL << 60)
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#define DBR_TYPE_CQ_ARMENA (0x7ULL << 60)
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#define DBR_TYPE_SRQ_ARMENA (0x8ULL << 60)
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#define DBR_TYPE_CQ_CUTOFF_ACK (0x9ULL << 60)
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#define DBR_TYPE_NQ (0xaULL << 60)
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#define DBR_TYPE_NQ_ARM (0xbULL << 60)
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#define DBR_TYPE_NULL (0xfULL << 60)
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#define INVALID_HW_RING_ID ((u16)-1)
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/* The hardware supports certain page sizes. Use the supported page sizes
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@ -505,6 +537,9 @@ struct rx_tpa_end_cmp_ext {
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(!!((agg)->rx_agg_cmp_v & cpu_to_le32(RX_AGG_CMP_V)) == \
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!((raw_cons) & bp->cp_bit))
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#define NQ_CMP_VALID(nqcmp, raw_cons) \
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(!!((nqcmp)->v & cpu_to_le32(NQ_CN_V)) == !((raw_cons) & bp->cp_bit))
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#define TX_CMP_TYPE(txcmp) \
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(le32_to_cpu((txcmp)->tx_cmp_flags_type) & CMP_TYPE)
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@ -577,9 +612,13 @@ struct bnxt_sw_rx_agg_bd {
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dma_addr_t mapping;
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};
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struct bnxt_ring_struct {
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struct bnxt_ring_mem_info {
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int nr_pages;
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int page_size;
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u32 flags;
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#define BNXT_RMEM_VALID_PTE_FLAG 1
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#define BNXT_RMEM_RING_PTE_FLAG 2
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void **pg_arr;
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dma_addr_t *dma_arr;
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@ -588,12 +627,17 @@ struct bnxt_ring_struct {
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int vmem_size;
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void **vmem;
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};
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struct bnxt_ring_struct {
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struct bnxt_ring_mem_info ring_mem;
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u16 fw_ring_id; /* Ring id filled by Chimp FW */
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union {
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u16 grp_idx;
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u16 map_idx; /* Used by cmpl rings */
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};
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u32 handle;
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u8 queue_id;
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};
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@ -609,12 +653,20 @@ struct tx_push_buffer {
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u32 data[25];
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};
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struct bnxt_db_info {
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void __iomem *doorbell;
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union {
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u64 db_key64;
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u32 db_key32;
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};
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};
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struct bnxt_tx_ring_info {
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struct bnxt_napi *bnapi;
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u16 tx_prod;
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u16 tx_cons;
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u16 txq_index;
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void __iomem *tx_doorbell;
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struct bnxt_db_info tx_db;
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struct tx_bd *tx_desc_ring[MAX_TX_PAGES];
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struct bnxt_sw_tx_bd *tx_buf_ring;
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@ -631,6 +683,42 @@ struct bnxt_tx_ring_info {
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struct bnxt_ring_struct tx_ring_struct;
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};
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#define BNXT_LEGACY_COAL_CMPL_PARAMS \
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(RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN | \
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RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX | \
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RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET | \
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RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE | \
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RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR | \
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RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT | \
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RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR | \
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RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT | \
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RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT)
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#define BNXT_COAL_CMPL_ENABLES \
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(RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR | \
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RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR | \
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RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX | \
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RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT)
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#define BNXT_COAL_CMPL_MIN_TMR_ENABLE \
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RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN
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#define BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE \
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RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT
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struct bnxt_coal_cap {
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u32 cmpl_params;
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u32 nq_params;
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u16 num_cmpl_dma_aggr_max;
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u16 num_cmpl_dma_aggr_during_int_max;
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u16 cmpl_aggr_dma_tmr_max;
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u16 cmpl_aggr_dma_tmr_during_int_max;
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u16 int_lat_tmr_min_max;
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u16 int_lat_tmr_max_max;
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u16 num_cmpl_aggr_int_max;
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u16 timer_units;
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};
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struct bnxt_coal {
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u16 coal_ticks;
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u16 coal_ticks_irq;
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@ -675,8 +763,8 @@ struct bnxt_rx_ring_info {
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u16 rx_agg_prod;
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u16 rx_sw_agg_prod;
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u16 rx_next_cons;
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void __iomem *rx_doorbell;
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void __iomem *rx_agg_doorbell;
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struct bnxt_db_info rx_db;
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struct bnxt_db_info rx_agg_db;
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struct bpf_prog *xdp_prog;
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@ -703,8 +791,12 @@ struct bnxt_rx_ring_info {
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};
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struct bnxt_cp_ring_info {
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struct bnxt_napi *bnapi;
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u32 cp_raw_cons;
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void __iomem *cp_doorbell;
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struct bnxt_db_info cp_db;
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u8 had_work_done:1;
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u8 has_more_work:1;
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struct bnxt_coal rx_ring_coal;
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u64 rx_packets;
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@ -713,7 +805,10 @@ struct bnxt_cp_ring_info {
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struct net_dim dim;
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struct tx_cmp *cp_desc_ring[MAX_CP_PAGES];
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union {
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struct tx_cmp *cp_desc_ring[MAX_CP_PAGES];
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struct nqe_cn *nq_desc_ring[MAX_CP_PAGES];
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};
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dma_addr_t cp_desc_mapping[MAX_CP_PAGES];
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@ -723,6 +818,10 @@ struct bnxt_cp_ring_info {
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u64 rx_l4_csum_errors;
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struct bnxt_ring_struct cp_ring_struct;
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struct bnxt_cp_ring_info *cp_ring_arr[2];
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#define BNXT_RX_HDL 0
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#define BNXT_TX_HDL 1
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};
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struct bnxt_napi {
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@ -736,6 +835,9 @@ struct bnxt_napi {
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void (*tx_int)(struct bnxt *, struct bnxt_napi *,
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int);
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int tx_pkts;
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u8 events;
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u32 flags;
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#define BNXT_NAPI_FLAG_XDP 0x1
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@ -755,6 +857,7 @@ struct bnxt_irq {
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#define HWRM_RING_ALLOC_RX 0x2
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#define HWRM_RING_ALLOC_AGG 0x4
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#define HWRM_RING_ALLOC_CMPL 0x8
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#define HWRM_RING_ALLOC_NQ 0x10
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#define INVALID_STATS_CTX_ID -1
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@ -768,7 +871,7 @@ struct bnxt_ring_grp_info {
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struct bnxt_vnic_info {
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u16 fw_vnic_id; /* returned by Chimp during alloc */
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#define BNXT_MAX_CTX_PER_VNIC 2
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#define BNXT_MAX_CTX_PER_VNIC 8
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u16 fw_rss_cos_lb_ctx[BNXT_MAX_CTX_PER_VNIC];
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u16 fw_l2_ctx_id;
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#define BNXT_MAX_UC_ADDRS 4
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@ -1069,6 +1172,55 @@ struct bnxt_vf_rep {
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struct bnxt_vf_rep_stats tx_stats;
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};
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#define PTU_PTE_VALID 0x1UL
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#define PTU_PTE_LAST 0x2UL
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#define PTU_PTE_NEXT_TO_LAST 0x4UL
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#define MAX_CTX_PAGES (BNXT_PAGE_SIZE / 8)
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struct bnxt_ctx_pg_info {
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u32 entries;
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void *ctx_pg_arr[MAX_CTX_PAGES];
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dma_addr_t ctx_dma_arr[MAX_CTX_PAGES];
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struct bnxt_ring_mem_info ring_mem;
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};
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struct bnxt_ctx_mem_info {
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u32 qp_max_entries;
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u16 qp_min_qp1_entries;
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u16 qp_max_l2_entries;
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u16 qp_entry_size;
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u16 srq_max_l2_entries;
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u32 srq_max_entries;
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u16 srq_entry_size;
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u16 cq_max_l2_entries;
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u32 cq_max_entries;
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u16 cq_entry_size;
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u16 vnic_max_vnic_entries;
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u16 vnic_max_ring_table_entries;
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u16 vnic_entry_size;
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u32 stat_max_entries;
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u16 stat_entry_size;
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u16 tqm_entry_size;
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u32 tqm_min_entries_per_ring;
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u32 tqm_max_entries_per_ring;
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u32 mrav_max_entries;
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u16 mrav_entry_size;
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u16 tim_entry_size;
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u32 tim_max_entries;
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u8 tqm_entries_multiple;
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u32 flags;
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#define BNXT_CTX_FLAG_INITED 0x01
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struct bnxt_ctx_pg_info qp_mem;
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struct bnxt_ctx_pg_info srq_mem;
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struct bnxt_ctx_pg_info cq_mem;
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struct bnxt_ctx_pg_info vnic_mem;
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struct bnxt_ctx_pg_info stat_mem;
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struct bnxt_ctx_pg_info *tqm_mem[9];
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};
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struct bnxt {
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void __iomem *bar0;
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void __iomem *bar1;
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@ -1098,6 +1250,8 @@ struct bnxt {
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#define CHIP_NUM_5745X 0xd730
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#define CHIP_NUM_57500 0x1750
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#define CHIP_NUM_58802 0xd802
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#define CHIP_NUM_58804 0xd804
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#define CHIP_NUM_58808 0xd808
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@ -1144,6 +1298,7 @@ struct bnxt {
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atomic_t intr_sem;
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u32 flags;
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#define BNXT_FLAG_CHIP_P5 0x1
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#define BNXT_FLAG_VF 0x2
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#define BNXT_FLAG_LRO 0x4
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#ifdef CONFIG_INET
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@ -1190,15 +1345,24 @@ struct bnxt {
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#define BNXT_SINGLE_PF(bp) (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp))
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#define BNXT_CHIP_TYPE_NITRO_A0(bp) ((bp)->flags & BNXT_FLAG_CHIP_NITRO_A0)
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#define BNXT_RX_PAGE_MODE(bp) ((bp)->flags & BNXT_FLAG_RX_PAGE_MODE)
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#define BNXT_SUPPORTS_TPA(bp) (!BNXT_CHIP_TYPE_NITRO_A0(bp) && \
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!(bp->flags & BNXT_FLAG_CHIP_P5))
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/* Chip class phase 4 and later */
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#define BNXT_CHIP_P4_PLUS(bp) \
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/* Chip class phase 5 */
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#define BNXT_CHIP_P5(bp) \
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((bp)->chip_num == CHIP_NUM_57500)
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/* Chip class phase 4.x */
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#define BNXT_CHIP_P4(bp) \
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(BNXT_CHIP_NUM_57X1X((bp)->chip_num) || \
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BNXT_CHIP_NUM_5745X((bp)->chip_num) || \
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BNXT_CHIP_NUM_588XX((bp)->chip_num) || \
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(BNXT_CHIP_NUM_58700((bp)->chip_num) && \
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!BNXT_CHIP_TYPE_NITRO_A0(bp)))
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#define BNXT_CHIP_P4_PLUS(bp) \
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(BNXT_CHIP_P4(bp) || BNXT_CHIP_P5(bp))
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struct bnxt_en_dev *edev;
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struct bnxt_en_dev * (*ulp_probe)(struct net_device *);
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@ -1261,6 +1425,8 @@ struct bnxt {
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u8 max_lltc; /* lossless TCs */
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struct bnxt_queue_info q_info[BNXT_MAX_QUEUE];
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u8 tc_to_qidx[BNXT_MAX_QUEUE];
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u8 q_ids[BNXT_MAX_QUEUE];
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u8 max_q;
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unsigned int current_interval;
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#define BNXT_TIMER_INTERVAL HZ
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@ -1305,12 +1471,17 @@ struct bnxt {
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struct rx_port_stats *hw_rx_port_stats;
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struct tx_port_stats *hw_tx_port_stats;
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struct rx_port_stats_ext *hw_rx_port_stats_ext;
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struct rx_port_stats_ext *hw_tx_port_stats_ext;
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dma_addr_t hw_rx_port_stats_map;
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dma_addr_t hw_tx_port_stats_map;
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dma_addr_t hw_rx_port_stats_ext_map;
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dma_addr_t hw_tx_port_stats_ext_map;
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int hw_port_stats_size;
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u16 fw_rx_stats_ext_size;
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u16 fw_tx_stats_ext_size;
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u16 hwrm_max_req_len;
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u16 hwrm_max_ext_req_len;
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int hwrm_cmd_timeout;
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struct mutex hwrm_cmd_lock; /* serialize hwrm messages */
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struct hwrm_ver_get_output ver_resp;
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@ -1328,11 +1499,10 @@ struct bnxt {
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u8 port_count;
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u16 br_mode;
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struct bnxt_coal_cap coal_cap;
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struct bnxt_coal rx_coal;
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struct bnxt_coal tx_coal;
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#define BNXT_USEC_TO_COAL_TIMER(x) ((x) * 25 / 2)
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u32 stats_coal_ticks;
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#define BNXT_DEF_STATS_COAL_TICKS 1000000
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#define BNXT_MIN_STATS_COAL_TICKS 250000
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@ -1360,6 +1530,7 @@ struct bnxt {
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struct bnxt_hw_resc hw_resc;
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struct bnxt_pf_info pf;
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struct bnxt_ctx_mem_info *ctx;
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#ifdef CONFIG_BNXT_SRIOV
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int nr_vfs;
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struct bnxt_vf_info vf;
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@ -1374,6 +1545,11 @@ struct bnxt {
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struct mutex sriov_lock;
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#endif
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|
||||
#if BITS_PER_LONG == 32
|
||||
/* ensure atomic 64-bit doorbell writes on 32-bit systems. */
|
||||
spinlock_t db_lock;
|
||||
#endif
|
||||
|
||||
#define BNXT_NTP_FLTR_MAX_FLTR 4096
|
||||
#define BNXT_NTP_FLTR_HASH_SIZE 512
|
||||
#define BNXT_NTP_FLTR_HASH_MASK (BNXT_NTP_FLTR_HASH_SIZE - 1)
|
||||
@ -1425,6 +1601,9 @@ struct bnxt {
|
||||
#define BNXT_RX_STATS_EXT_OFFSET(counter) \
|
||||
(offsetof(struct rx_port_stats_ext, counter) / 8)
|
||||
|
||||
#define BNXT_TX_STATS_EXT_OFFSET(counter) \
|
||||
(offsetof(struct tx_port_stats_ext, counter) / 8)
|
||||
|
||||
#define I2C_DEV_ADDR_A0 0xa0
|
||||
#define I2C_DEV_ADDR_A2 0xa2
|
||||
#define SFF_DIAG_SUPPORT_OFFSET 0x5c
|
||||
@ -1443,21 +1622,46 @@ static inline u32 bnxt_tx_avail(struct bnxt *bp, struct bnxt_tx_ring_info *txr)
|
||||
((txr->tx_prod - txr->tx_cons) & bp->tx_ring_mask);
|
||||
}
|
||||
|
||||
#if BITS_PER_LONG == 32
|
||||
#define writeq(val64, db) \
|
||||
do { \
|
||||
spin_lock(&bp->db_lock); \
|
||||
writel((val64) & 0xffffffff, db); \
|
||||
writel((val64) >> 32, (db) + 4); \
|
||||
spin_unlock(&bp->db_lock); \
|
||||
} while (0)
|
||||
|
||||
#define writeq_relaxed writeq
|
||||
#endif
|
||||
|
||||
/* For TX and RX ring doorbells with no ordering guarantee*/
|
||||
static inline void bnxt_db_write_relaxed(struct bnxt *bp, void __iomem *db,
|
||||
u32 val)
|
||||
static inline void bnxt_db_write_relaxed(struct bnxt *bp,
|
||||
struct bnxt_db_info *db, u32 idx)
|
||||
{
|
||||
writel_relaxed(val, db);
|
||||
if (bp->flags & BNXT_FLAG_DOUBLE_DB)
|
||||
writel_relaxed(val, db);
|
||||
if (bp->flags & BNXT_FLAG_CHIP_P5) {
|
||||
writeq_relaxed(db->db_key64 | idx, db->doorbell);
|
||||
} else {
|
||||
u32 db_val = db->db_key32 | idx;
|
||||
|
||||
writel_relaxed(db_val, db->doorbell);
|
||||
if (bp->flags & BNXT_FLAG_DOUBLE_DB)
|
||||
writel_relaxed(db_val, db->doorbell);
|
||||
}
|
||||
}
|
||||
|
||||
/* For TX and RX ring doorbells */
|
||||
static inline void bnxt_db_write(struct bnxt *bp, void __iomem *db, u32 val)
|
||||
static inline void bnxt_db_write(struct bnxt *bp, struct bnxt_db_info *db,
|
||||
u32 idx)
|
||||
{
|
||||
writel(val, db);
|
||||
if (bp->flags & BNXT_FLAG_DOUBLE_DB)
|
||||
writel(val, db);
|
||||
if (bp->flags & BNXT_FLAG_CHIP_P5) {
|
||||
writeq(db->db_key64 | idx, db->doorbell);
|
||||
} else {
|
||||
u32 db_val = db->db_key32 | idx;
|
||||
|
||||
writel(db_val, db->doorbell);
|
||||
if (bp->flags & BNXT_FLAG_DOUBLE_DB)
|
||||
writel(db_val, db->doorbell);
|
||||
}
|
||||
}
|
||||
|
||||
extern const u16 bnxt_lhint_arr[];
|
||||
|
||||
@ -148,6 +148,65 @@ reset_coalesce:
|
||||
#define BNXT_RX_STATS_EXT_ENTRY(counter) \
|
||||
{ BNXT_RX_STATS_EXT_OFFSET(counter), __stringify(counter) }
|
||||
|
||||
#define BNXT_TX_STATS_EXT_ENTRY(counter) \
|
||||
{ BNXT_TX_STATS_EXT_OFFSET(counter), __stringify(counter) }
|
||||
|
||||
#define BNXT_RX_STATS_EXT_PFC_ENTRY(n) \
|
||||
BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_duration_us), \
|
||||
BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_transitions)
|
||||
|
||||
#define BNXT_TX_STATS_EXT_PFC_ENTRY(n) \
|
||||
BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_duration_us), \
|
||||
BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_transitions)
|
||||
|
||||
#define BNXT_RX_STATS_EXT_PFC_ENTRIES \
|
||||
BNXT_RX_STATS_EXT_PFC_ENTRY(0), \
|
||||
BNXT_RX_STATS_EXT_PFC_ENTRY(1), \
|
||||
BNXT_RX_STATS_EXT_PFC_ENTRY(2), \
|
||||
BNXT_RX_STATS_EXT_PFC_ENTRY(3), \
|
||||
BNXT_RX_STATS_EXT_PFC_ENTRY(4), \
|
||||
BNXT_RX_STATS_EXT_PFC_ENTRY(5), \
|
||||
BNXT_RX_STATS_EXT_PFC_ENTRY(6), \
|
||||
BNXT_RX_STATS_EXT_PFC_ENTRY(7)
|
||||
|
||||
#define BNXT_TX_STATS_EXT_PFC_ENTRIES \
|
||||
BNXT_TX_STATS_EXT_PFC_ENTRY(0), \
|
||||
BNXT_TX_STATS_EXT_PFC_ENTRY(1), \
|
||||
BNXT_TX_STATS_EXT_PFC_ENTRY(2), \
|
||||
BNXT_TX_STATS_EXT_PFC_ENTRY(3), \
|
||||
BNXT_TX_STATS_EXT_PFC_ENTRY(4), \
|
||||
BNXT_TX_STATS_EXT_PFC_ENTRY(5), \
|
||||
BNXT_TX_STATS_EXT_PFC_ENTRY(6), \
|
||||
BNXT_TX_STATS_EXT_PFC_ENTRY(7)
|
||||
|
||||
#define BNXT_RX_STATS_EXT_COS_ENTRY(n) \
|
||||
BNXT_RX_STATS_EXT_ENTRY(rx_bytes_cos##n), \
|
||||
BNXT_RX_STATS_EXT_ENTRY(rx_packets_cos##n)
|
||||
|
||||
#define BNXT_TX_STATS_EXT_COS_ENTRY(n) \
|
||||
BNXT_TX_STATS_EXT_ENTRY(tx_bytes_cos##n), \
|
||||
BNXT_TX_STATS_EXT_ENTRY(tx_packets_cos##n)
|
||||
|
||||
#define BNXT_RX_STATS_EXT_COS_ENTRIES \
|
||||
BNXT_RX_STATS_EXT_COS_ENTRY(0), \
|
||||
BNXT_RX_STATS_EXT_COS_ENTRY(1), \
|
||||
BNXT_RX_STATS_EXT_COS_ENTRY(2), \
|
||||
BNXT_RX_STATS_EXT_COS_ENTRY(3), \
|
||||
BNXT_RX_STATS_EXT_COS_ENTRY(4), \
|
||||
BNXT_RX_STATS_EXT_COS_ENTRY(5), \
|
||||
BNXT_RX_STATS_EXT_COS_ENTRY(6), \
|
||||
BNXT_RX_STATS_EXT_COS_ENTRY(7) \
|
||||
|
||||
#define BNXT_TX_STATS_EXT_COS_ENTRIES \
|
||||
BNXT_TX_STATS_EXT_COS_ENTRY(0), \
|
||||
BNXT_TX_STATS_EXT_COS_ENTRY(1), \
|
||||
BNXT_TX_STATS_EXT_COS_ENTRY(2), \
|
||||
BNXT_TX_STATS_EXT_COS_ENTRY(3), \
|
||||
BNXT_TX_STATS_EXT_COS_ENTRY(4), \
|
||||
BNXT_TX_STATS_EXT_COS_ENTRY(5), \
|
||||
BNXT_TX_STATS_EXT_COS_ENTRY(6), \
|
||||
BNXT_TX_STATS_EXT_COS_ENTRY(7) \
|
||||
|
||||
enum {
|
||||
RX_TOTAL_DISCARDS,
|
||||
TX_TOTAL_DISCARDS,
|
||||
@ -256,11 +315,20 @@ static const struct {
|
||||
BNXT_RX_STATS_EXT_ENTRY(resume_pause_events),
|
||||
BNXT_RX_STATS_EXT_ENTRY(continuous_roce_pause_events),
|
||||
BNXT_RX_STATS_EXT_ENTRY(resume_roce_pause_events),
|
||||
BNXT_RX_STATS_EXT_COS_ENTRIES,
|
||||
BNXT_RX_STATS_EXT_PFC_ENTRIES,
|
||||
};
|
||||
|
||||
static const struct {
|
||||
long offset;
|
||||
char string[ETH_GSTRING_LEN];
|
||||
} bnxt_tx_port_stats_ext_arr[] = {
|
||||
BNXT_TX_STATS_EXT_COS_ENTRIES,
|
||||
BNXT_TX_STATS_EXT_PFC_ENTRIES,
|
||||
};
|
||||
|
||||
#define BNXT_NUM_SW_FUNC_STATS ARRAY_SIZE(bnxt_sw_func_stats)
|
||||
#define BNXT_NUM_PORT_STATS ARRAY_SIZE(bnxt_port_stats_arr)
|
||||
#define BNXT_NUM_PORT_STATS_EXT ARRAY_SIZE(bnxt_port_stats_ext_arr)
|
||||
|
||||
static int bnxt_get_num_stats(struct bnxt *bp)
|
||||
{
|
||||
@ -272,7 +340,8 @@ static int bnxt_get_num_stats(struct bnxt *bp)
|
||||
num_stats += BNXT_NUM_PORT_STATS;
|
||||
|
||||
if (bp->flags & BNXT_FLAG_PORT_STATS_EXT)
|
||||
num_stats += BNXT_NUM_PORT_STATS_EXT;
|
||||
num_stats += bp->fw_rx_stats_ext_size +
|
||||
bp->fw_tx_stats_ext_size;
|
||||
|
||||
return num_stats;
|
||||
}
|
||||
@ -334,12 +403,17 @@ static void bnxt_get_ethtool_stats(struct net_device *dev,
|
||||
}
|
||||
}
|
||||
if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) {
|
||||
__le64 *port_stats_ext = (__le64 *)bp->hw_rx_port_stats_ext;
|
||||
__le64 *rx_port_stats_ext = (__le64 *)bp->hw_rx_port_stats_ext;
|
||||
__le64 *tx_port_stats_ext = (__le64 *)bp->hw_tx_port_stats_ext;
|
||||
|
||||
for (i = 0; i < BNXT_NUM_PORT_STATS_EXT; i++, j++) {
|
||||
buf[j] = le64_to_cpu(*(port_stats_ext +
|
||||
for (i = 0; i < bp->fw_rx_stats_ext_size; i++, j++) {
|
||||
buf[j] = le64_to_cpu(*(rx_port_stats_ext +
|
||||
bnxt_port_stats_ext_arr[i].offset));
|
||||
}
|
||||
for (i = 0; i < bp->fw_tx_stats_ext_size; i++, j++) {
|
||||
buf[j] = le64_to_cpu(*(tx_port_stats_ext +
|
||||
bnxt_tx_port_stats_ext_arr[i].offset));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@ -407,10 +481,15 @@ static void bnxt_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
|
||||
}
|
||||
}
|
||||
if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) {
|
||||
for (i = 0; i < BNXT_NUM_PORT_STATS_EXT; i++) {
|
||||
for (i = 0; i < bp->fw_rx_stats_ext_size; i++) {
|
||||
strcpy(buf, bnxt_port_stats_ext_arr[i].string);
|
||||
buf += ETH_GSTRING_LEN;
|
||||
}
|
||||
for (i = 0; i < bp->fw_tx_stats_ext_size; i++) {
|
||||
strcpy(buf,
|
||||
bnxt_tx_port_stats_ext_arr[i].string);
|
||||
buf += ETH_GSTRING_LEN;
|
||||
}
|
||||
}
|
||||
break;
|
||||
case ETH_SS_TEST:
|
||||
@ -2419,11 +2498,11 @@ static int bnxt_hwrm_phy_loopback(struct bnxt *bp, bool enable, bool ext)
|
||||
return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
|
||||
}
|
||||
|
||||
static int bnxt_rx_loopback(struct bnxt *bp, struct bnxt_napi *bnapi,
|
||||
static int bnxt_rx_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
|
||||
u32 raw_cons, int pkt_size)
|
||||
{
|
||||
struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
|
||||
struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
|
||||
struct bnxt_napi *bnapi = cpr->bnapi;
|
||||
struct bnxt_rx_ring_info *rxr;
|
||||
struct bnxt_sw_rx_bd *rx_buf;
|
||||
struct rx_cmp *rxcmp;
|
||||
u16 cp_cons, cons;
|
||||
@ -2431,6 +2510,7 @@ static int bnxt_rx_loopback(struct bnxt *bp, struct bnxt_napi *bnapi,
|
||||
u32 len;
|
||||
int i;
|
||||
|
||||
rxr = bnapi->rx_ring;
|
||||
cp_cons = RING_CMP(raw_cons);
|
||||
rxcmp = (struct rx_cmp *)
|
||||
&cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
|
||||
@ -2451,17 +2531,15 @@ static int bnxt_rx_loopback(struct bnxt *bp, struct bnxt_napi *bnapi,
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bnxt_poll_loopback(struct bnxt *bp, int pkt_size)
|
||||
static int bnxt_poll_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
|
||||
int pkt_size)
|
||||
{
|
||||
struct bnxt_napi *bnapi = bp->bnapi[0];
|
||||
struct bnxt_cp_ring_info *cpr;
|
||||
struct tx_cmp *txcmp;
|
||||
int rc = -EIO;
|
||||
u32 raw_cons;
|
||||
u32 cons;
|
||||
int i;
|
||||
|
||||
cpr = &bnapi->cp_ring;
|
||||
raw_cons = cpr->cp_raw_cons;
|
||||
for (i = 0; i < 200; i++) {
|
||||
cons = RING_CMP(raw_cons);
|
||||
@ -2477,7 +2555,7 @@ static int bnxt_poll_loopback(struct bnxt *bp, int pkt_size)
|
||||
*/
|
||||
dma_rmb();
|
||||
if (TX_CMP_TYPE(txcmp) == CMP_TYPE_RX_L2_CMP) {
|
||||
rc = bnxt_rx_loopback(bp, bnapi, raw_cons, pkt_size);
|
||||
rc = bnxt_rx_loopback(bp, cpr, raw_cons, pkt_size);
|
||||
raw_cons = NEXT_RAW_CMP(raw_cons);
|
||||
raw_cons = NEXT_RAW_CMP(raw_cons);
|
||||
break;
|
||||
@ -2491,12 +2569,14 @@ static int bnxt_poll_loopback(struct bnxt *bp, int pkt_size)
|
||||
static int bnxt_run_loopback(struct bnxt *bp)
|
||||
{
|
||||
struct bnxt_tx_ring_info *txr = &bp->tx_ring[0];
|
||||
struct bnxt_cp_ring_info *cpr;
|
||||
int pkt_size, i = 0;
|
||||
struct sk_buff *skb;
|
||||
dma_addr_t map;
|
||||
u8 *data;
|
||||
int rc;
|
||||
|
||||
cpr = &txr->bnapi->cp_ring;
|
||||
pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_copy_thresh);
|
||||
skb = netdev_alloc_skb(bp->dev, pkt_size);
|
||||
if (!skb)
|
||||
@ -2520,8 +2600,8 @@ static int bnxt_run_loopback(struct bnxt *bp)
|
||||
/* Sync BD data before updating doorbell */
|
||||
wmb();
|
||||
|
||||
bnxt_db_write(bp, txr->tx_doorbell, DB_KEY_TX | txr->tx_prod);
|
||||
rc = bnxt_poll_loopback(bp, pkt_size);
|
||||
bnxt_db_write(bp, &txr->tx_db, txr->tx_prod);
|
||||
rc = bnxt_poll_loopback(bp, cpr, pkt_size);
|
||||
|
||||
dma_unmap_single(&bp->pdev->dev, map, pkt_size, PCI_DMA_TODEVICE);
|
||||
dev_kfree_skb(skb);
|
||||
|
||||
@ -37,6 +37,8 @@ struct hwrm_resp_hdr {
|
||||
#define TLV_TYPE_HWRM_REQUEST 0x1UL
|
||||
#define TLV_TYPE_HWRM_RESPONSE 0x2UL
|
||||
#define TLV_TYPE_ROCE_SP_COMMAND 0x3UL
|
||||
#define TLV_TYPE_QUERY_ROCE_CC_GEN1 0x4UL
|
||||
#define TLV_TYPE_MODIFY_ROCE_CC_GEN1 0x5UL
|
||||
#define TLV_TYPE_ENGINE_CKV_DEVICE_SERIAL_NUMBER 0x8001UL
|
||||
#define TLV_TYPE_ENGINE_CKV_NONCE 0x8002UL
|
||||
#define TLV_TYPE_ENGINE_CKV_IV 0x8003UL
|
||||
@ -186,6 +188,7 @@ struct cmd_nums {
|
||||
#define HWRM_TUNNEL_DST_PORT_QUERY 0xa0UL
|
||||
#define HWRM_TUNNEL_DST_PORT_ALLOC 0xa1UL
|
||||
#define HWRM_TUNNEL_DST_PORT_FREE 0xa2UL
|
||||
#define HWRM_STAT_CTX_ENG_QUERY 0xafUL
|
||||
#define HWRM_STAT_CTX_ALLOC 0xb0UL
|
||||
#define HWRM_STAT_CTX_FREE 0xb1UL
|
||||
#define HWRM_STAT_CTX_QUERY 0xb2UL
|
||||
@ -235,6 +238,7 @@ struct cmd_nums {
|
||||
#define HWRM_CFA_PAIR_INFO 0x10fUL
|
||||
#define HWRM_FW_IPC_MSG 0x110UL
|
||||
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO 0x111UL
|
||||
#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE 0x112UL
|
||||
#define HWRM_ENGINE_CKV_HELLO 0x12dUL
|
||||
#define HWRM_ENGINE_CKV_STATUS 0x12eUL
|
||||
#define HWRM_ENGINE_CKV_CKEK_ADD 0x12fUL
|
||||
@ -295,6 +299,7 @@ struct cmd_nums {
|
||||
#define HWRM_DBG_COREDUMP_RETRIEVE 0xff19UL
|
||||
#define HWRM_DBG_FW_CLI 0xff1aUL
|
||||
#define HWRM_DBG_I2C_CMD 0xff1bUL
|
||||
#define HWRM_DBG_RING_INFO_GET 0xff1cUL
|
||||
#define HWRM_NVM_FACTORY_DEFAULTS 0xffeeUL
|
||||
#define HWRM_NVM_VALIDATE_OPTION 0xffefUL
|
||||
#define HWRM_NVM_FLUSH 0xfff0UL
|
||||
@ -320,20 +325,21 @@ struct cmd_nums {
|
||||
/* ret_codes (size:64b/8B) */
|
||||
struct ret_codes {
|
||||
__le16 error_code;
|
||||
#define HWRM_ERR_CODE_SUCCESS 0x0UL
|
||||
#define HWRM_ERR_CODE_FAIL 0x1UL
|
||||
#define HWRM_ERR_CODE_INVALID_PARAMS 0x2UL
|
||||
#define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED 0x3UL
|
||||
#define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR 0x4UL
|
||||
#define HWRM_ERR_CODE_INVALID_FLAGS 0x5UL
|
||||
#define HWRM_ERR_CODE_INVALID_ENABLES 0x6UL
|
||||
#define HWRM_ERR_CODE_UNSUPPORTED_TLV 0x7UL
|
||||
#define HWRM_ERR_CODE_NO_BUFFER 0x8UL
|
||||
#define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR 0x9UL
|
||||
#define HWRM_ERR_CODE_HWRM_ERROR 0xfUL
|
||||
#define HWRM_ERR_CODE_UNKNOWN_ERR 0xfffeUL
|
||||
#define HWRM_ERR_CODE_CMD_NOT_SUPPORTED 0xffffUL
|
||||
#define HWRM_ERR_CODE_LAST HWRM_ERR_CODE_CMD_NOT_SUPPORTED
|
||||
#define HWRM_ERR_CODE_SUCCESS 0x0UL
|
||||
#define HWRM_ERR_CODE_FAIL 0x1UL
|
||||
#define HWRM_ERR_CODE_INVALID_PARAMS 0x2UL
|
||||
#define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED 0x3UL
|
||||
#define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR 0x4UL
|
||||
#define HWRM_ERR_CODE_INVALID_FLAGS 0x5UL
|
||||
#define HWRM_ERR_CODE_INVALID_ENABLES 0x6UL
|
||||
#define HWRM_ERR_CODE_UNSUPPORTED_TLV 0x7UL
|
||||
#define HWRM_ERR_CODE_NO_BUFFER 0x8UL
|
||||
#define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR 0x9UL
|
||||
#define HWRM_ERR_CODE_HWRM_ERROR 0xfUL
|
||||
#define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE 0x8000UL
|
||||
#define HWRM_ERR_CODE_UNKNOWN_ERR 0xfffeUL
|
||||
#define HWRM_ERR_CODE_CMD_NOT_SUPPORTED 0xffffUL
|
||||
#define HWRM_ERR_CODE_LAST HWRM_ERR_CODE_CMD_NOT_SUPPORTED
|
||||
__le16 unused_0[3];
|
||||
};
|
||||
|
||||
@ -355,10 +361,10 @@ struct hwrm_err_output {
|
||||
#define HW_HASH_KEY_SIZE 40
|
||||
#define HWRM_RESP_VALID_KEY 1
|
||||
#define HWRM_VERSION_MAJOR 1
|
||||
#define HWRM_VERSION_MINOR 9
|
||||
#define HWRM_VERSION_UPDATE 2
|
||||
#define HWRM_VERSION_RSVD 25
|
||||
#define HWRM_VERSION_STR "1.9.2.25"
|
||||
#define HWRM_VERSION_MINOR 10
|
||||
#define HWRM_VERSION_UPDATE 0
|
||||
#define HWRM_VERSION_RSVD 3
|
||||
#define HWRM_VERSION_STR "1.10.0.3"
|
||||
|
||||
/* hwrm_ver_get_input (size:192b/24B) */
|
||||
struct hwrm_ver_get_input {
|
||||
@ -396,10 +402,15 @@ struct hwrm_ver_get_output {
|
||||
u8 netctrl_fw_bld_8b;
|
||||
u8 netctrl_fw_rsvd_8b;
|
||||
__le32 dev_caps_cfg;
|
||||
#define VER_GET_RESP_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED 0x1UL
|
||||
#define VER_GET_RESP_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED 0x2UL
|
||||
#define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED 0x4UL
|
||||
#define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED 0x8UL
|
||||
#define VER_GET_RESP_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED 0x1UL
|
||||
#define VER_GET_RESP_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED 0x2UL
|
||||
#define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED 0x4UL
|
||||
#define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED 0x8UL
|
||||
#define VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED 0x10UL
|
||||
#define VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED 0x20UL
|
||||
#define VER_GET_RESP_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED 0x40UL
|
||||
#define VER_GET_RESP_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED 0x80UL
|
||||
#define VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED 0x100UL
|
||||
u8 roce_fw_maj_8b;
|
||||
u8 roce_fw_min_8b;
|
||||
u8 roce_fw_bld_8b;
|
||||
@ -528,6 +539,7 @@ struct hwrm_async_event_cmpl {
|
||||
#define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED 0x5UL
|
||||
#define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL
|
||||
#define ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE 0x7UL
|
||||
#define ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY 0x8UL
|
||||
#define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD 0x10UL
|
||||
#define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD 0x11UL
|
||||
#define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT 0x12UL
|
||||
@ -539,6 +551,7 @@ struct hwrm_async_event_cmpl {
|
||||
#define ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE 0x33UL
|
||||
#define ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE 0x34UL
|
||||
#define ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE 0x35UL
|
||||
#define ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED 0x36UL
|
||||
#define ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 0xffUL
|
||||
#define ASYNC_EVENT_CMPL_EVENT_ID_LAST ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR
|
||||
__le32 event_data2;
|
||||
@ -652,10 +665,11 @@ struct hwrm_async_event_cmpl_vf_cfg_change {
|
||||
u8 timestamp_lo;
|
||||
__le16 timestamp_hi;
|
||||
__le32 event_data1;
|
||||
#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE 0x1UL
|
||||
#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE 0x2UL
|
||||
#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE 0x4UL
|
||||
#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE 0x8UL
|
||||
#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE 0x1UL
|
||||
#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE 0x2UL
|
||||
#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE 0x4UL
|
||||
#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE 0x8UL
|
||||
#define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE 0x10UL
|
||||
};
|
||||
|
||||
/* hwrm_func_reset_input (size:192b/24B) */
|
||||
@ -852,6 +866,7 @@ struct hwrm_func_qcaps_output {
|
||||
#define FUNC_QCAPS_RESP_FLAGS_ADOPTED_PF_SUPPORTED 0x20000UL
|
||||
#define FUNC_QCAPS_RESP_FLAGS_ADMIN_PF_SUPPORTED 0x40000UL
|
||||
#define FUNC_QCAPS_RESP_FLAGS_LINK_ADMIN_STATUS_SUPPORTED 0x80000UL
|
||||
#define FUNC_QCAPS_RESP_FLAGS_WCB_PUSH_MODE 0x100000UL
|
||||
u8 mac_address[6];
|
||||
__le16 max_rsscos_ctx;
|
||||
__le16 max_cmpl_rings;
|
||||
@ -903,6 +918,7 @@ struct hwrm_func_qcfg_output {
|
||||
#define FUNC_QCFG_RESP_FLAGS_STD_TX_RING_MODE_ENABLED 0x8UL
|
||||
#define FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED 0x10UL
|
||||
#define FUNC_QCFG_RESP_FLAGS_MULTI_HOST 0x20UL
|
||||
#define FUNC_QCFG_RESP_FLAGS_TRUSTED_VF 0x40UL
|
||||
u8 mac_address[6];
|
||||
__le16 pci_id;
|
||||
__le16 alloc_rsscos_ctx;
|
||||
@ -1014,6 +1030,7 @@ struct hwrm_func_cfg_input {
|
||||
#define FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x40000UL
|
||||
#define FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x80000UL
|
||||
#define FUNC_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x100000UL
|
||||
#define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_ENABLE 0x200000UL
|
||||
__le32 enables;
|
||||
#define FUNC_CFG_REQ_ENABLES_MTU 0x1UL
|
||||
#define FUNC_CFG_REQ_ENABLES_MRU 0x2UL
|
||||
@ -1214,9 +1231,10 @@ struct hwrm_func_drv_rgtr_input {
|
||||
__le16 target_id;
|
||||
__le64 resp_addr;
|
||||
__le32 flags;
|
||||
#define FUNC_DRV_RGTR_REQ_FLAGS_FWD_ALL_MODE 0x1UL
|
||||
#define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE 0x2UL
|
||||
#define FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE 0x4UL
|
||||
#define FUNC_DRV_RGTR_REQ_FLAGS_FWD_ALL_MODE 0x1UL
|
||||
#define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE 0x2UL
|
||||
#define FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE 0x4UL
|
||||
#define FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE 0x8UL
|
||||
__le32 enables;
|
||||
#define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE 0x1UL
|
||||
#define FUNC_DRV_RGTR_REQ_ENABLES_VER 0x2UL
|
||||
@ -1416,7 +1434,9 @@ struct hwrm_func_resource_qcaps_output {
|
||||
__le16 min_hw_ring_grps;
|
||||
__le16 max_hw_ring_grps;
|
||||
__le16 max_tx_scheduler_inputs;
|
||||
u8 unused_0[7];
|
||||
__le16 flags;
|
||||
#define FUNC_RESOURCE_QCAPS_RESP_FLAGS_MIN_GUARANTEED 0x1UL
|
||||
u8 unused_0[5];
|
||||
u8 valid;
|
||||
};
|
||||
|
||||
@ -1445,7 +1465,9 @@ struct hwrm_func_vf_resource_cfg_input {
|
||||
__le16 max_stat_ctx;
|
||||
__le16 min_hw_ring_grps;
|
||||
__le16 max_hw_ring_grps;
|
||||
u8 unused_0[4];
|
||||
__le16 flags;
|
||||
#define FUNC_VF_RESOURCE_CFG_REQ_FLAGS_MIN_GUARANTEED 0x1UL
|
||||
u8 unused_0[2];
|
||||
};
|
||||
|
||||
/* hwrm_func_vf_resource_cfg_output (size:256b/32B) */
|
||||
@ -1503,7 +1525,8 @@ struct hwrm_func_backing_store_qcaps_output {
|
||||
__le16 mrav_entry_size;
|
||||
__le16 tim_entry_size;
|
||||
__le32 tim_max_entries;
|
||||
u8 unused_0[3];
|
||||
u8 unused_0[2];
|
||||
u8 tqm_entries_multiple;
|
||||
u8 valid;
|
||||
};
|
||||
|
||||
@ -1917,6 +1940,7 @@ struct hwrm_port_phy_cfg_input {
|
||||
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB 0x190UL
|
||||
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB 0x1f4UL
|
||||
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB 0x3e8UL
|
||||
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_200GB 0x7d0UL
|
||||
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 0xffffUL
|
||||
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB
|
||||
u8 auto_mode;
|
||||
@ -1947,6 +1971,7 @@ struct hwrm_port_phy_cfg_input {
|
||||
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB 0x190UL
|
||||
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB 0x1f4UL
|
||||
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100GB 0x3e8UL
|
||||
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_200GB 0x7d0UL
|
||||
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 0xffffUL
|
||||
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_LAST PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB
|
||||
__le16 auto_link_speed_mask;
|
||||
@ -1964,6 +1989,7 @@ struct hwrm_port_phy_cfg_input {
|
||||
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100GB 0x800UL
|
||||
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL
|
||||
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MB 0x2000UL
|
||||
#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_200GB 0x4000UL
|
||||
u8 wirespeed;
|
||||
#define PORT_PHY_CFG_REQ_WIRESPEED_OFF 0x0UL
|
||||
#define PORT_PHY_CFG_REQ_WIRESPEED_ON 0x1UL
|
||||
@ -2048,6 +2074,7 @@ struct hwrm_port_phy_qcfg_output {
|
||||
#define PORT_PHY_QCFG_RESP_LINK_SPEED_40GB 0x190UL
|
||||
#define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB 0x1f4UL
|
||||
#define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB 0x3e8UL
|
||||
#define PORT_PHY_QCFG_RESP_LINK_SPEED_200GB 0x7d0UL
|
||||
#define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 0xffffUL
|
||||
#define PORT_PHY_QCFG_RESP_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_LINK_SPEED_10MB
|
||||
u8 duplex_cfg;
|
||||
@ -2072,6 +2099,7 @@ struct hwrm_port_phy_qcfg_output {
|
||||
#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB 0x800UL
|
||||
#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MBHD 0x1000UL
|
||||
#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MB 0x2000UL
|
||||
#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_200GB 0x4000UL
|
||||
__le16 force_link_speed;
|
||||
#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100MB 0x1UL
|
||||
#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_1GB 0xaUL
|
||||
@ -2083,6 +2111,7 @@ struct hwrm_port_phy_qcfg_output {
|
||||
#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_40GB 0x190UL
|
||||
#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_50GB 0x1f4UL
|
||||
#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100GB 0x3e8UL
|
||||
#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_200GB 0x7d0UL
|
||||
#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 0xffffUL
|
||||
#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB
|
||||
u8 auto_mode;
|
||||
@ -2107,6 +2136,7 @@ struct hwrm_port_phy_qcfg_output {
|
||||
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_40GB 0x190UL
|
||||
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_50GB 0x1f4UL
|
||||
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100GB 0x3e8UL
|
||||
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_200GB 0x7d0UL
|
||||
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 0xffffUL
|
||||
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB
|
||||
__le16 auto_link_speed_mask;
|
||||
@ -2124,6 +2154,7 @@ struct hwrm_port_phy_qcfg_output {
|
||||
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100GB 0x800UL
|
||||
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL
|
||||
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MB 0x2000UL
|
||||
#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_200GB 0x4000UL
|
||||
u8 wirespeed;
|
||||
#define PORT_PHY_QCFG_RESP_WIRESPEED_OFF 0x0UL
|
||||
#define PORT_PHY_QCFG_RESP_WIRESPEED_ON 0x1UL
|
||||
@ -2178,7 +2209,11 @@ struct hwrm_port_phy_qcfg_output {
|
||||
#define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASET 0x19UL
|
||||
#define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASESX 0x1aUL
|
||||
#define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX 0x1bUL
|
||||
#define PORT_PHY_QCFG_RESP_PHY_TYPE_LAST PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX
|
||||
#define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR4 0x1cUL
|
||||
#define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR4 0x1dUL
|
||||
#define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR4 0x1eUL
|
||||
#define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4 0x1fUL
|
||||
#define PORT_PHY_QCFG_RESP_PHY_TYPE_LAST PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4
|
||||
u8 media_type;
|
||||
#define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN 0x0UL
|
||||
#define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP 0x1UL
|
||||
@ -2644,7 +2679,8 @@ struct hwrm_port_qstats_ext_output {
|
||||
__le16 tx_stat_size;
|
||||
__le16 rx_stat_size;
|
||||
__le16 total_active_cos_queues;
|
||||
u8 unused_0;
|
||||
u8 flags;
|
||||
#define PORT_QSTATS_EXT_RESP_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED 0x1UL
|
||||
u8 valid;
|
||||
};
|
||||
|
||||
@ -2685,7 +2721,9 @@ struct hwrm_port_clr_stats_input {
|
||||
__le16 target_id;
|
||||
__le64 resp_addr;
|
||||
__le16 port_id;
|
||||
u8 unused_0[6];
|
||||
u8 flags;
|
||||
#define PORT_CLR_STATS_REQ_FLAGS_ROCE_COUNTERS 0x1UL
|
||||
u8 unused_0[5];
|
||||
};
|
||||
|
||||
/* hwrm_port_clr_stats_output (size:128b/16B) */
|
||||
@ -4574,7 +4612,9 @@ struct hwrm_ring_alloc_input {
|
||||
#define RING_ALLOC_REQ_RING_TYPE_RX_AGG 0x4UL
|
||||
#define RING_ALLOC_REQ_RING_TYPE_NQ 0x5UL
|
||||
#define RING_ALLOC_REQ_RING_TYPE_LAST RING_ALLOC_REQ_RING_TYPE_NQ
|
||||
u8 unused_0[3];
|
||||
u8 unused_0;
|
||||
__le16 flags;
|
||||
#define RING_ALLOC_REQ_FLAGS_RX_SOP_PAD 0x1UL
|
||||
__le64 page_tbl_addr;
|
||||
__le32 fbo;
|
||||
u8 page_size;
|
||||
@ -4838,13 +4878,19 @@ struct hwrm_cfa_l2_filter_alloc_input {
|
||||
__le16 target_id;
|
||||
__le64 resp_addr;
|
||||
__le32 flags;
|
||||
#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH 0x1UL
|
||||
#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_TX 0x0UL
|
||||
#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 0x1UL
|
||||
#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX
|
||||
#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x2UL
|
||||
#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_DROP 0x4UL
|
||||
#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST 0x8UL
|
||||
#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH 0x1UL
|
||||
#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_TX 0x0UL
|
||||
#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 0x1UL
|
||||
#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX
|
||||
#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x2UL
|
||||
#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_DROP 0x4UL
|
||||
#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST 0x8UL
|
||||
#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_MASK 0x30UL
|
||||
#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_SFT 4
|
||||
#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 4)
|
||||
#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 4)
|
||||
#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 4)
|
||||
#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE
|
||||
__le32 enables;
|
||||
#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x1UL
|
||||
#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK 0x2UL
|
||||
@ -4901,6 +4947,8 @@ struct hwrm_cfa_l2_filter_alloc_input {
|
||||
#define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL
|
||||
#define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL
|
||||
#define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
|
||||
#define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
|
||||
#define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
|
||||
#define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
|
||||
#define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
|
||||
u8 unused_4;
|
||||
@ -4958,11 +5006,17 @@ struct hwrm_cfa_l2_filter_cfg_input {
|
||||
__le16 target_id;
|
||||
__le64 resp_addr;
|
||||
__le32 flags;
|
||||
#define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH 0x1UL
|
||||
#define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_TX 0x0UL
|
||||
#define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 0x1UL
|
||||
#define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX
|
||||
#define CFA_L2_FILTER_CFG_REQ_FLAGS_DROP 0x2UL
|
||||
#define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH 0x1UL
|
||||
#define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_TX 0x0UL
|
||||
#define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 0x1UL
|
||||
#define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX
|
||||
#define CFA_L2_FILTER_CFG_REQ_FLAGS_DROP 0x2UL
|
||||
#define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_MASK 0xcUL
|
||||
#define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_SFT 2
|
||||
#define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 2)
|
||||
#define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 2)
|
||||
#define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 2)
|
||||
#define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE
|
||||
__le32 enables;
|
||||
#define CFA_L2_FILTER_CFG_REQ_ENABLES_DST_ID 0x1UL
|
||||
#define CFA_L2_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL
|
||||
@ -5064,6 +5118,8 @@ struct hwrm_cfa_tunnel_filter_alloc_input {
|
||||
#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL
|
||||
#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL
|
||||
#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
|
||||
#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
|
||||
#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
|
||||
#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
|
||||
#define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
|
||||
u8 tunnel_flags;
|
||||
@ -5140,7 +5196,7 @@ struct hwrm_vxlan_ipv6_hdr {
|
||||
__be32 dest_ip_addr[4];
|
||||
};
|
||||
|
||||
/* hwrm_cfa_encap_data_vxlan (size:576b/72B) */
|
||||
/* hwrm_cfa_encap_data_vxlan (size:640b/80B) */
|
||||
struct hwrm_cfa_encap_data_vxlan {
|
||||
u8 src_mac_addr[6];
|
||||
__le16 unused_0;
|
||||
@ -5159,6 +5215,10 @@ struct hwrm_cfa_encap_data_vxlan {
|
||||
__be16 src_port;
|
||||
__be16 dst_port;
|
||||
__be32 vni;
|
||||
u8 hdr_rsvd0[3];
|
||||
u8 hdr_rsvd1;
|
||||
u8 hdr_flags;
|
||||
u8 unused[3];
|
||||
};
|
||||
|
||||
/* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */
|
||||
@ -5171,15 +5231,18 @@ struct hwrm_cfa_encap_record_alloc_input {
|
||||
__le32 flags;
|
||||
#define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL
|
||||
u8 encap_type;
|
||||
#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN 0x1UL
|
||||
#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_NVGRE 0x2UL
|
||||
#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2GRE 0x3UL
|
||||
#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPIP 0x4UL
|
||||
#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_GENEVE 0x5UL
|
||||
#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_MPLS 0x6UL
|
||||
#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VLAN 0x7UL
|
||||
#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE 0x8UL
|
||||
#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_LAST CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE
|
||||
#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN 0x1UL
|
||||
#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_NVGRE 0x2UL
|
||||
#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2GRE 0x3UL
|
||||
#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPIP 0x4UL
|
||||
#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_GENEVE 0x5UL
|
||||
#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_MPLS 0x6UL
|
||||
#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VLAN 0x7UL
|
||||
#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE 0x8UL
|
||||
#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_V4 0x9UL
|
||||
#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE_V1 0xaUL
|
||||
#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2_ETYPE 0xbUL
|
||||
#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_LAST CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2_ETYPE
|
||||
u8 unused_0[3];
|
||||
__le32 encap_data[20];
|
||||
};
|
||||
@ -5273,6 +5336,8 @@ struct hwrm_cfa_ntuple_filter_alloc_input {
|
||||
#define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL
|
||||
#define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL
|
||||
#define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
|
||||
#define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
|
||||
#define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
|
||||
#define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
|
||||
#define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
|
||||
u8 pri_hint;
|
||||
@ -5404,6 +5469,8 @@ struct hwrm_cfa_decap_filter_alloc_input {
|
||||
#define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL
|
||||
#define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL
|
||||
#define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
|
||||
#define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
|
||||
#define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
|
||||
#define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
|
||||
#define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
|
||||
u8 unused_0;
|
||||
@ -5476,19 +5543,22 @@ struct hwrm_cfa_flow_alloc_input {
|
||||
__le16 target_id;
|
||||
__le64 resp_addr;
|
||||
__le16 flags;
|
||||
#define CFA_FLOW_ALLOC_REQ_FLAGS_TUNNEL 0x1UL
|
||||
#define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_MASK 0x6UL
|
||||
#define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_SFT 1
|
||||
#define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_NONE (0x0UL << 1)
|
||||
#define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_ONE (0x1UL << 1)
|
||||
#define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO (0x2UL << 1)
|
||||
#define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_LAST CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO
|
||||
#define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_MASK 0x38UL
|
||||
#define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_SFT 3
|
||||
#define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_L2 (0x0UL << 3)
|
||||
#define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV4 (0x1UL << 3)
|
||||
#define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 (0x2UL << 3)
|
||||
#define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_LAST CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6
|
||||
#define CFA_FLOW_ALLOC_REQ_FLAGS_TUNNEL 0x1UL
|
||||
#define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_MASK 0x6UL
|
||||
#define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_SFT 1
|
||||
#define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_NONE (0x0UL << 1)
|
||||
#define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_ONE (0x1UL << 1)
|
||||
#define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO (0x2UL << 1)
|
||||
#define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_LAST CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO
|
||||
#define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_MASK 0x38UL
|
||||
#define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_SFT 3
|
||||
#define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_L2 (0x0UL << 3)
|
||||
#define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV4 (0x1UL << 3)
|
||||
#define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 (0x2UL << 3)
|
||||
#define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_LAST CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6
|
||||
#define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_TX 0x40UL
|
||||
#define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_RX 0x80UL
|
||||
#define CFA_FLOW_ALLOC_REQ_FLAGS_MATCH_VXLAN_IP_VNI 0x100UL
|
||||
__le16 src_fid;
|
||||
__le32 tunnel_handle;
|
||||
__le16 action_flags;
|
||||
@ -5502,6 +5572,7 @@ struct hwrm_cfa_flow_alloc_input {
|
||||
#define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_IPV4_ADDRESS 0x80UL
|
||||
#define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_L2_HEADER_REWRITE 0x100UL
|
||||
#define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TTL_DECREMENT 0x200UL
|
||||
#define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL_IP 0x400UL
|
||||
__le16 dst_fid;
|
||||
__be16 l2_rewrite_vlan_tpid;
|
||||
__be16 l2_rewrite_vlan_tci;
|
||||
@ -5525,21 +5596,38 @@ struct hwrm_cfa_flow_alloc_input {
|
||||
__be16 nat_port;
|
||||
__be16 l2_rewrite_smac[3];
|
||||
u8 ip_proto;
|
||||
u8 unused_0;
|
||||
u8 tunnel_type;
|
||||
#define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
|
||||
#define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
|
||||
#define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL
|
||||
#define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL
|
||||
#define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL
|
||||
#define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL
|
||||
#define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL
|
||||
#define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL
|
||||
#define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL
|
||||
#define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
|
||||
#define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
|
||||
#define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
|
||||
#define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
|
||||
#define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
|
||||
};
|
||||
|
||||
/* hwrm_cfa_flow_alloc_output (size:128b/16B) */
|
||||
/* hwrm_cfa_flow_alloc_output (size:256b/32B) */
|
||||
struct hwrm_cfa_flow_alloc_output {
|
||||
__le16 error_code;
|
||||
__le16 req_type;
|
||||
__le16 seq_id;
|
||||
__le16 resp_len;
|
||||
__le16 flow_handle;
|
||||
u8 unused_0[5];
|
||||
u8 unused_0[2];
|
||||
__le32 flow_id;
|
||||
__le64 ext_flow_handle;
|
||||
u8 unused_1[7];
|
||||
u8 valid;
|
||||
};
|
||||
|
||||
/* hwrm_cfa_flow_free_input (size:192b/24B) */
|
||||
/* hwrm_cfa_flow_free_input (size:256b/32B) */
|
||||
struct hwrm_cfa_flow_free_input {
|
||||
__le16 req_type;
|
||||
__le16 cmpl_ring;
|
||||
@ -5548,6 +5636,7 @@ struct hwrm_cfa_flow_free_input {
|
||||
__le64 resp_addr;
|
||||
__le16 flow_handle;
|
||||
u8 unused_0[6];
|
||||
__le64 ext_flow_handle;
|
||||
};
|
||||
|
||||
/* hwrm_cfa_flow_free_output (size:256b/32B) */
|
||||
@ -5562,7 +5651,7 @@ struct hwrm_cfa_flow_free_output {
|
||||
u8 valid;
|
||||
};
|
||||
|
||||
/* hwrm_cfa_flow_stats_input (size:320b/40B) */
|
||||
/* hwrm_cfa_flow_stats_input (size:640b/80B) */
|
||||
struct hwrm_cfa_flow_stats_input {
|
||||
__le16 req_type;
|
||||
__le16 cmpl_ring;
|
||||
@ -5581,6 +5670,16 @@ struct hwrm_cfa_flow_stats_input {
|
||||
__le16 flow_handle_8;
|
||||
__le16 flow_handle_9;
|
||||
u8 unused_0[2];
|
||||
__le32 flow_id_0;
|
||||
__le32 flow_id_1;
|
||||
__le32 flow_id_2;
|
||||
__le32 flow_id_3;
|
||||
__le32 flow_id_4;
|
||||
__le32 flow_id_5;
|
||||
__le32 flow_id_6;
|
||||
__le32 flow_id_7;
|
||||
__le32 flow_id_8;
|
||||
__le32 flow_id_9;
|
||||
};
|
||||
|
||||
/* hwrm_cfa_flow_stats_output (size:1408b/176B) */
|
||||
@ -5670,7 +5769,8 @@ struct hwrm_tunnel_dst_port_query_input {
|
||||
#define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GENEVE 0x5UL
|
||||
#define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
|
||||
#define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
|
||||
#define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_IPGRE_V1
|
||||
#define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
|
||||
#define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_L2_ETYPE
|
||||
u8 unused_0[7];
|
||||
};
|
||||
|
||||
@ -5698,7 +5798,8 @@ struct hwrm_tunnel_dst_port_alloc_input {
|
||||
#define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL
|
||||
#define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
|
||||
#define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
|
||||
#define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1
|
||||
#define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
|
||||
#define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE
|
||||
u8 unused_0;
|
||||
__be16 tunnel_dst_port_val;
|
||||
u8 unused_1[4];
|
||||
@ -5727,7 +5828,8 @@ struct hwrm_tunnel_dst_port_free_input {
|
||||
#define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE 0x5UL
|
||||
#define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
|
||||
#define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
|
||||
#define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_IPGRE_V1
|
||||
#define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
|
||||
#define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_L2_ETYPE
|
||||
u8 unused_0;
|
||||
__le16 tunnel_dst_port_id;
|
||||
u8 unused_1[4];
|
||||
@ -5932,10 +6034,11 @@ struct hwrm_fw_reset_input {
|
||||
#define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT 0x7UL
|
||||
#define FW_RESET_REQ_EMBEDDED_PROC_TYPE_LAST FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT
|
||||
u8 selfrst_status;
|
||||
#define FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE 0x0UL
|
||||
#define FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP 0x1UL
|
||||
#define FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST 0x2UL
|
||||
#define FW_RESET_REQ_SELFRST_STATUS_LAST FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST
|
||||
#define FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE 0x0UL
|
||||
#define FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP 0x1UL
|
||||
#define FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST 0x2UL
|
||||
#define FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL
|
||||
#define FW_RESET_REQ_SELFRST_STATUS_LAST FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE
|
||||
u8 host_idx;
|
||||
u8 unused_0[5];
|
||||
};
|
||||
@ -5947,10 +6050,11 @@ struct hwrm_fw_reset_output {
|
||||
__le16 seq_id;
|
||||
__le16 resp_len;
|
||||
u8 selfrst_status;
|
||||
#define FW_RESET_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL
|
||||
#define FW_RESET_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL
|
||||
#define FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL
|
||||
#define FW_RESET_RESP_SELFRST_STATUS_LAST FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST
|
||||
#define FW_RESET_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL
|
||||
#define FW_RESET_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL
|
||||
#define FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL
|
||||
#define FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL
|
||||
#define FW_RESET_RESP_SELFRST_STATUS_LAST FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE
|
||||
u8 unused_0[6];
|
||||
u8 valid;
|
||||
};
|
||||
@ -6498,6 +6602,34 @@ struct hwrm_dbg_coredump_retrieve_output {
|
||||
u8 valid;
|
||||
};
|
||||
|
||||
/* hwrm_dbg_ring_info_get_input (size:192b/24B) */
|
||||
struct hwrm_dbg_ring_info_get_input {
|
||||
__le16 req_type;
|
||||
__le16 cmpl_ring;
|
||||
__le16 seq_id;
|
||||
__le16 target_id;
|
||||
__le64 resp_addr;
|
||||
u8 ring_type;
|
||||
#define DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL 0x0UL
|
||||
#define DBG_RING_INFO_GET_REQ_RING_TYPE_TX 0x1UL
|
||||
#define DBG_RING_INFO_GET_REQ_RING_TYPE_RX 0x2UL
|
||||
#define DBG_RING_INFO_GET_REQ_RING_TYPE_LAST DBG_RING_INFO_GET_REQ_RING_TYPE_RX
|
||||
u8 unused_0[3];
|
||||
__le32 fw_ring_id;
|
||||
};
|
||||
|
||||
/* hwrm_dbg_ring_info_get_output (size:192b/24B) */
|
||||
struct hwrm_dbg_ring_info_get_output {
|
||||
__le16 error_code;
|
||||
__le16 req_type;
|
||||
__le16 seq_id;
|
||||
__le16 resp_len;
|
||||
__le32 producer_index;
|
||||
__le32 consumer_index;
|
||||
u8 unused_0[7];
|
||||
u8 valid;
|
||||
};
|
||||
|
||||
/* hwrm_nvm_read_input (size:320b/40B) */
|
||||
struct hwrm_nvm_read_input {
|
||||
__le16 req_type;
|
||||
|
||||
@ -63,7 +63,7 @@ void bnxt_tx_int_xdp(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts)
|
||||
tx_buf = &txr->tx_buf_ring[last_tx_cons];
|
||||
rx_prod = tx_buf->rx_prod;
|
||||
}
|
||||
bnxt_db_write(bp, rxr->rx_doorbell, DB_KEY_RX | rx_prod);
|
||||
bnxt_db_write(bp, &rxr->rx_db, rx_prod);
|
||||
}
|
||||
|
||||
/* returns the following:
|
||||
|
||||
Loading…
Reference in New Issue
Block a user