forked from Minki/linux
media: ti-vpe: cal: Add per platform data support
First this patch adds a method to access the CTRL_CORE_CAMERRX_CONTROL register to use the syscon mechanism. For backward compatibility we also handle using the existing camerrx_control "reg" entry if a syscon node is not found. In addition the register bit layout for the CTRL_CORE_CAMERRX_CONTROL changes depending on the device. In order to support this we need to use a register access scheme based on data configuration instead of using static macro. In this case we make use of the regmap facility and create data set based on the various device and phy available. Signed-off-by: Benoit Parrot <bparrot@ti.com> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
This commit is contained in:
Benoit Parrot
Mauro Carvalho Chehab
parent
5e51dd3525
commit
65ee4280f1
@ -14,6 +14,8 @@
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#include <linux/delay.h>
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#include <linux/pm_runtime.h>
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#include <linux/slab.h>
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#include <linux/mfd/syscon.h>
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#include <linux/regmap.h>
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#include <linux/videodev2.h>
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#include <linux/of_device.h>
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#include <linux/of_graph.h>
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@ -220,15 +222,6 @@ struct cal_dmaqueue {
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int ini_jiffies;
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};
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struct cm_data {
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void __iomem *base;
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struct resource *res;
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unsigned int camerrx_control;
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struct platform_device *pdev;
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};
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struct cc_data {
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void __iomem *base;
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struct resource *res;
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@ -236,6 +229,59 @@ struct cc_data {
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struct platform_device *pdev;
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};
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/* CTRL_CORE_CAMERRX_CONTROL register field id */
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enum cal_camerarx_field {
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F_CTRLCLKEN,
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F_CAMMODE,
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F_LANEENABLE,
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F_CSI_MODE,
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F_MAX_FIELDS,
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};
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struct cal_csi2_phy {
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struct regmap_field *fields[F_MAX_FIELDS];
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struct reg_field *base_fields;
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const int num_lanes;
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};
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struct cal_data {
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const int num_csi2_phy;
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struct cal_csi2_phy *csi2_phy_core;
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const unsigned int flags;
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};
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static struct reg_field dra72x_ctrl_core_csi0_reg_fields[F_MAX_FIELDS] = {
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[F_CTRLCLKEN] = REG_FIELD(0, 10, 10),
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[F_CAMMODE] = REG_FIELD(0, 11, 12),
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[F_LANEENABLE] = REG_FIELD(0, 13, 16),
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[F_CSI_MODE] = REG_FIELD(0, 17, 17),
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};
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static struct reg_field dra72x_ctrl_core_csi1_reg_fields[F_MAX_FIELDS] = {
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[F_CTRLCLKEN] = REG_FIELD(0, 0, 0),
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[F_CAMMODE] = REG_FIELD(0, 1, 2),
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[F_LANEENABLE] = REG_FIELD(0, 3, 4),
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[F_CSI_MODE] = REG_FIELD(0, 5, 5),
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};
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static struct cal_csi2_phy dra72x_cal_csi_phy[] = {
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{
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.base_fields = dra72x_ctrl_core_csi0_reg_fields,
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.num_lanes = 4,
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},
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{
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.base_fields = dra72x_ctrl_core_csi1_reg_fields,
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.num_lanes = 2,
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},
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};
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static const struct cal_data dra72x_cal_data = {
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.csi2_phy_core = dra72x_cal_csi_phy,
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.num_csi2_phy = ARRAY_SIZE(dra72x_cal_csi_phy),
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};
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/*
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* there is one cal_dev structure in the driver, it is shared by
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* all instances.
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@ -247,8 +293,15 @@ struct cal_dev {
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struct platform_device *pdev;
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struct v4l2_device v4l2_dev;
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/* Controller flags for special cases */
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unsigned int flags;
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const struct cal_data *data;
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/* Control Module handle */
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struct cm_data *cm;
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struct regmap *syscon_camerrx;
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u32 syscon_camerrx_offset;
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/* Camera Core Module handle */
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struct cc_data *cc[CAL_NUM_CSI2_PORTS];
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@ -359,73 +412,113 @@ static inline void set_field(u32 *valp, u32 field, u32 mask)
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*valp = val;
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}
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/*
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* Control Module block access
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*/
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static struct cm_data *cm_create(struct cal_dev *dev)
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static u32 cal_data_get_phy_max_lanes(struct cal_ctx *ctx)
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{
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struct cal_dev *dev = ctx->dev;
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u32 phy_id = ctx->csi2_port - 1;
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return dev->data->csi2_phy_core[phy_id].num_lanes;
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}
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static u32 cal_data_get_num_csi2_phy(struct cal_dev *dev)
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{
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return dev->data->num_csi2_phy;
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}
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static int cal_camerarx_regmap_init(struct cal_dev *dev)
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{
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struct reg_field *field;
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struct cal_csi2_phy *phy;
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int i, j;
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if (!dev->data)
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return -EINVAL;
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for (i = 0; i < cal_data_get_num_csi2_phy(dev); i++) {
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phy = &dev->data->csi2_phy_core[i];
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for (j = 0; j < F_MAX_FIELDS; j++) {
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field = &phy->base_fields[j];
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/*
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* Here we update the reg offset with the
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* value found in DT
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*/
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field->reg = dev->syscon_camerrx_offset;
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phy->fields[j] =
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devm_regmap_field_alloc(&dev->pdev->dev,
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dev->syscon_camerrx,
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*field);
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if (IS_ERR(phy->fields[j])) {
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cal_err(dev, "Unable to allocate regmap fields\n");
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return PTR_ERR(phy->fields[j]);
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}
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}
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}
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return 0;
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}
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static const struct regmap_config cal_regmap_config = {
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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};
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static struct regmap *cal_get_camerarx_regmap(struct cal_dev *dev)
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{
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struct platform_device *pdev = dev->pdev;
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struct cm_data *cm;
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struct regmap *regmap;
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void __iomem *base;
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u32 reg_io_width;
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struct regmap_config r_config = cal_regmap_config;
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struct resource *res;
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cm = devm_kzalloc(&pdev->dev, sizeof(*cm), GFP_KERNEL);
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if (!cm)
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return ERR_PTR(-ENOMEM);
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cm->res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
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"camerrx_control");
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cm->base = devm_ioremap_resource(&pdev->dev, cm->res);
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if (IS_ERR(cm->base)) {
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
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"camerrx_control");
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base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(base)) {
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cal_err(dev, "failed to ioremap\n");
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return ERR_CAST(cm->base);
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return ERR_CAST(base);
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}
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cal_dbg(1, dev, "ioresource %s at %pa - %pa\n",
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cm->res->name, &cm->res->start, &cm->res->end);
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res->name, &res->start, &res->end);
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return cm;
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reg_io_width = 4;
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r_config.reg_stride = reg_io_width;
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r_config.val_bits = reg_io_width * 8;
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r_config.max_register = resource_size(res) - reg_io_width;
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regmap = regmap_init_mmio(NULL, base, &r_config);
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if (IS_ERR(regmap))
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pr_err("regmap init failed\n");
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return regmap;
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}
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/*
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* Control Module CAMERARX block access
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*/
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static void camerarx_phy_enable(struct cal_ctx *ctx)
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{
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u32 val;
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struct cal_csi2_phy *phy;
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u32 phy_id = ctx->csi2_port - 1;
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u32 max_lanes;
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if (!ctx->dev->cm->base) {
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ctx_err(ctx, "cm not mapped\n");
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return;
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}
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val = reg_read(ctx->dev->cm, CM_CTRL_CORE_CAMERRX_CONTROL);
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if (ctx->csi2_port == 1) {
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set_field(&val, 1, CM_CAMERRX_CTRL_CSI0_CTRLCLKEN_MASK);
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set_field(&val, 0, CM_CAMERRX_CTRL_CSI0_CAMMODE_MASK);
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/* enable all lanes by default */
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set_field(&val, 0xf, CM_CAMERRX_CTRL_CSI0_LANEENABLE_MASK);
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set_field(&val, 1, CM_CAMERRX_CTRL_CSI0_MODE_MASK);
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} else if (ctx->csi2_port == 2) {
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set_field(&val, 1, CM_CAMERRX_CTRL_CSI1_CTRLCLKEN_MASK);
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set_field(&val, 0, CM_CAMERRX_CTRL_CSI1_CAMMODE_MASK);
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/* enable all lanes by default */
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set_field(&val, 0x3, CM_CAMERRX_CTRL_CSI1_LANEENABLE_MASK);
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set_field(&val, 1, CM_CAMERRX_CTRL_CSI1_MODE_MASK);
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}
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reg_write(ctx->dev->cm, CM_CTRL_CORE_CAMERRX_CONTROL, val);
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phy = &ctx->dev->data->csi2_phy_core[phy_id];
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regmap_field_write(phy->fields[F_CAMMODE], 0);
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/* Always enable all lanes at the phy control level */
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max_lanes = (1 << cal_data_get_phy_max_lanes(ctx)) - 1;
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regmap_field_write(phy->fields[F_LANEENABLE], max_lanes);
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regmap_field_write(phy->fields[F_CSI_MODE], 1);
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regmap_field_write(phy->fields[F_CTRLCLKEN], 1);
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}
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static void camerarx_phy_disable(struct cal_ctx *ctx)
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{
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u32 val;
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struct cal_csi2_phy *phy;
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u32 phy_id = ctx->csi2_port - 1;
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if (!ctx->dev->cm->base) {
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ctx_err(ctx, "cm not mapped\n");
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return;
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}
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val = reg_read(ctx->dev->cm, CM_CTRL_CORE_CAMERRX_CONTROL);
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if (ctx->csi2_port == 1)
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set_field(&val, 0x0, CM_CAMERRX_CTRL_CSI0_CTRLCLKEN_MASK);
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else if (ctx->csi2_port == 2)
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set_field(&val, 0x0, CM_CAMERRX_CTRL_CSI1_CTRLCLKEN_MASK);
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reg_write(ctx->dev->cm, CM_CTRL_CORE_CAMERRX_CONTROL, val);
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phy = &ctx->dev->data->csi2_phy_core[phy_id];
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regmap_field_write(phy->fields[F_CTRLCLKEN], 0);
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}
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/*
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@ -508,12 +601,6 @@ static void cal_quickdump_regs(struct cal_dev *dev)
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resource_size(dev->ctx[1]->cc->res),
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false);
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}
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cal_info(dev, "CAMERRX_Control Registers @ %pa:\n",
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&dev->cm->res->start);
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print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 4,
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(__force const void *)dev->cm->base,
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resource_size(dev->cm->res), false);
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}
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/*
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@ -1804,10 +1891,15 @@ err_exit:
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return NULL;
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}
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static const struct of_device_id cal_of_match[];
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static int cal_probe(struct platform_device *pdev)
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{
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struct cal_dev *dev;
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struct cal_ctx *ctx;
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struct device_node *parent = pdev->dev.of_node;
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struct regmap *syscon_camerrx = NULL;
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u32 syscon_camerrx_offset = 0;
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int ret;
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int irq;
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int i;
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@ -1816,6 +1908,14 @@ static int cal_probe(struct platform_device *pdev)
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if (!dev)
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return -ENOMEM;
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dev->data = of_device_get_match_data(&pdev->dev);
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if (!dev->data) {
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dev_err(&pdev->dev, "Could not get feature data based on compatible version\n");
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return -ENODEV;
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}
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dev->flags = dev->data->flags;
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/* set pseudo v4l2 device name so we can use v4l2_printk */
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strscpy(dev->v4l2_dev.name, CAL_MODULE_NAME,
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sizeof(dev->v4l2_dev.name));
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@ -1823,6 +1923,38 @@ static int cal_probe(struct platform_device *pdev)
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/* save pdev pointer */
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dev->pdev = pdev;
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syscon_camerrx = syscon_regmap_lookup_by_phandle(parent,
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"ti,camerrx-control");
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ret = of_property_read_u32_index(parent, "ti,camerrx-control", 1,
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&syscon_camerrx_offset);
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if (IS_ERR(syscon_camerrx))
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ret = PTR_ERR(syscon_camerrx);
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if (ret) {
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dev_warn(&pdev->dev, "failed to get ti,camerrx-control: %d\n",
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ret);
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/*
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* Backward DTS compatibility.
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* If syscon entry is not present then check if the
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* camerrx_control resource is present.
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*/
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syscon_camerrx = cal_get_camerarx_regmap(dev);
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if (IS_ERR(syscon_camerrx)) {
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dev_err(&pdev->dev, "failed to get camerrx_control regmap\n");
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return PTR_ERR(syscon_camerrx);
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}
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/* In this case the base already point to the direct
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* CM register so no need for an offset
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*/
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syscon_camerrx_offset = 0;
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}
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dev->syscon_camerrx = syscon_camerrx;
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dev->syscon_camerrx_offset = syscon_camerrx_offset;
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ret = cal_camerarx_regmap_init(dev);
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if (ret)
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return ret;
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dev->res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
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"cal_top");
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dev->base = devm_ioremap_resource(&pdev->dev, dev->res);
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@ -1841,23 +1973,24 @@ static int cal_probe(struct platform_device *pdev)
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platform_set_drvdata(pdev, dev);
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dev->cm = cm_create(dev);
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if (IS_ERR(dev->cm))
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return PTR_ERR(dev->cm);
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dev->cc[0] = cc_create(dev, 0);
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if (IS_ERR(dev->cc[0]))
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return PTR_ERR(dev->cc[0]);
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dev->cc[1] = cc_create(dev, 1);
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if (IS_ERR(dev->cc[1]))
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return PTR_ERR(dev->cc[1]);
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if (cal_data_get_num_csi2_phy(dev) > 1) {
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dev->cc[1] = cc_create(dev, 1);
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if (IS_ERR(dev->cc[1]))
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return PTR_ERR(dev->cc[1]);
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} else {
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dev->cc[1] = NULL;
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}
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dev->ctx[0] = NULL;
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dev->ctx[1] = NULL;
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dev->ctx[0] = cal_create_instance(dev, 0);
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dev->ctx[1] = cal_create_instance(dev, 1);
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if (cal_data_get_num_csi2_phy(dev) > 1)
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dev->ctx[1] = cal_create_instance(dev, 1);
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if (!dev->ctx[0] && !dev->ctx[1]) {
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cal_err(dev, "Neither port is configured, no point in staying up\n");
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return -ENODEV;
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@ -1924,7 +2057,10 @@ static int cal_remove(struct platform_device *pdev)
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#if defined(CONFIG_OF)
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static const struct of_device_id cal_of_match[] = {
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{ .compatible = "ti,dra72-cal", },
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{
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.compatible = "ti,dra72-cal",
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.data = (void *)&dra72x_cal_data,
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},
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{},
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};
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MODULE_DEVICE_TABLE(of, cal_of_match);
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