forked from Minki/linux
intel_idle: Add AlderLake-N support
Similar to the other other AlderLake platforms, the C1 and C1E states on ADL-N are mutually exclusive. Only one of them can be enabled at a time. C1E is preferred on ADL-N for better energy efficiency. C6S is also supported on this platform. Its latency is far bigger than C6, but really close to C8 (PC8), thus it is not exposed as a separate state. Suggested-by: Baieswara Reddy Sagili <baieswara.reddy.sagili@intel.com> Suggested-by: Vinay Kumar <vinay.kumar@intel.com> Signed-off-by: Zhang Rui <rui.zhang@intel.com> [ rjw: Changelog edits ] Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
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@ -928,6 +928,51 @@ static struct cpuidle_state adl_l_cstates[] __initdata = {
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.enter = NULL }
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};
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static struct cpuidle_state adl_n_cstates[] __initdata = {
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{
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.name = "C1",
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.desc = "MWAIT 0x00",
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.flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_UNUSABLE,
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.exit_latency = 1,
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.target_residency = 1,
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.enter = &intel_idle,
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.enter_s2idle = intel_idle_s2idle, },
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{
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.name = "C1E",
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.desc = "MWAIT 0x01",
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.flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
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.exit_latency = 2,
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.target_residency = 4,
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.enter = &intel_idle,
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.enter_s2idle = intel_idle_s2idle, },
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{
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.name = "C6",
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.desc = "MWAIT 0x20",
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.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 195,
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.target_residency = 585,
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.enter = &intel_idle,
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.enter_s2idle = intel_idle_s2idle, },
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{
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.name = "C8",
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.desc = "MWAIT 0x40",
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.flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 260,
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.target_residency = 1040,
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.enter = &intel_idle,
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.enter_s2idle = intel_idle_s2idle, },
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{
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.name = "C10",
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.desc = "MWAIT 0x60",
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.flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 660,
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.target_residency = 1980,
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.enter = &intel_idle,
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.enter_s2idle = intel_idle_s2idle, },
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{
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.enter = NULL }
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};
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static struct cpuidle_state spr_cstates[] __initdata = {
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{
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.name = "C1",
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@ -1309,6 +1354,10 @@ static const struct idle_cpu idle_cpu_adl_l __initconst = {
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.state_table = adl_l_cstates,
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};
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static const struct idle_cpu idle_cpu_adl_n __initconst = {
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.state_table = adl_n_cstates,
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};
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static const struct idle_cpu idle_cpu_spr __initconst = {
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.state_table = spr_cstates,
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.disable_promotion_to_c1e = true,
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@ -1379,6 +1428,7 @@ static const struct x86_cpu_id intel_idle_ids[] __initconst = {
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X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, &idle_cpu_icx),
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X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE, &idle_cpu_adl),
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X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, &idle_cpu_adl_l),
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X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_N, &idle_cpu_adl_n),
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X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, &idle_cpu_spr),
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X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNL, &idle_cpu_knl),
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X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNM, &idle_cpu_knl),
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@ -1816,6 +1866,7 @@ static void __init intel_idle_init_cstates_icpu(struct cpuidle_driver *drv)
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break;
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case INTEL_FAM6_ALDERLAKE:
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case INTEL_FAM6_ALDERLAKE_L:
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case INTEL_FAM6_ALDERLAKE_N:
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adl_idle_state_table_update();
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break;
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}
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