forked from Minki/linux
bnx2x: Add new PHY 54616s
Signed-off-by: Yaniv Rosner <yanivr@broadcom.com> Signed-off-by: Vladislav Zolotarov <vladz@broadcom.com> Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@conan.davemloft.net>
This commit is contained in:
Yaniv Rosner
David S. Miller
parent
3c9ada227c
commit
6583e33bae
@ -134,6 +134,9 @@
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#define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
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#define LINK_20GTFD LINK_STATUS_SPEED_AND_DUPLEX_20GTFD
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#define LINK_20GXFD LINK_STATUS_SPEED_AND_DUPLEX_20GXFD
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/* */
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#define SFP_EEPROM_CON_TYPE_ADDR 0x2
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#define SFP_EEPROM_CON_TYPE_VAL_LC 0x7
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@ -2059,6 +2062,83 @@ static u32 bnx2x_get_emac_base(struct bnx2x *bp,
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}
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/******************************************************************/
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/* CL22 access functions */
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/******************************************************************/
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static int bnx2x_cl22_write(struct bnx2x *bp,
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struct bnx2x_phy *phy,
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u16 reg, u16 val)
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{
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u32 tmp, mode;
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u8 i;
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int rc = 0;
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/* Switch to CL22 */
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mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
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REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
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mode & ~EMAC_MDIO_MODE_CLAUSE_45);
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/* address */
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tmp = ((phy->addr << 21) | (reg << 16) | val |
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EMAC_MDIO_COMM_COMMAND_WRITE_22 |
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EMAC_MDIO_COMM_START_BUSY);
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REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
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for (i = 0; i < 50; i++) {
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udelay(10);
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tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
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if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
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udelay(5);
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break;
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}
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}
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if (tmp & EMAC_MDIO_COMM_START_BUSY) {
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DP(NETIF_MSG_LINK, "write phy register failed\n");
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rc = -EFAULT;
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}
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REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
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return rc;
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}
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static int bnx2x_cl22_read(struct bnx2x *bp,
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struct bnx2x_phy *phy,
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u16 reg, u16 *ret_val)
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{
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u32 val, mode;
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u16 i;
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int rc = 0;
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/* Switch to CL22 */
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mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
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REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
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mode & ~EMAC_MDIO_MODE_CLAUSE_45);
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/* address */
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val = ((phy->addr << 21) | (reg << 16) |
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EMAC_MDIO_COMM_COMMAND_READ_22 |
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EMAC_MDIO_COMM_START_BUSY);
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REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
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for (i = 0; i < 50; i++) {
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udelay(10);
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val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
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if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
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*ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
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udelay(5);
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break;
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}
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}
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if (val & EMAC_MDIO_COMM_START_BUSY) {
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DP(NETIF_MSG_LINK, "read phy register failed\n");
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*ret_val = 0;
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rc = -EFAULT;
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}
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REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
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return rc;
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}
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/******************************************************************/
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/* CL45 access functions */
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/******************************************************************/
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@ -2649,12 +2729,19 @@ static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy,
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vars->flow_ctrl = params->req_fc_auto_adv;
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else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
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ret = 1;
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if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616) {
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bnx2x_cl22_read(bp, phy,
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0x4, &ld_pause);
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bnx2x_cl22_read(bp, phy,
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0x5, &lp_pause);
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} else {
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bnx2x_cl45_read(bp, phy,
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MDIO_AN_DEVAD,
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MDIO_AN_REG_ADV_PAUSE, &ld_pause);
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bnx2x_cl45_read(bp, phy,
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MDIO_AN_DEVAD,
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MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
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}
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pause_result = (ld_pause &
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MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
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pause_result |= (lp_pause &
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@ -4653,8 +4740,13 @@ static u16 bnx2x_wait_reset_complete(struct bnx2x *bp,
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u16 cnt, ctrl;
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/* Wait for soft reset to get cleared up to 1 sec */
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for (cnt = 0; cnt < 1000; cnt++) {
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if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616)
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bnx2x_cl22_read(bp, phy,
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MDIO_PMA_REG_CTRL, &ctrl);
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else
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bnx2x_cl45_read(bp, phy,
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MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, &ctrl);
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MDIO_PMA_DEVAD,
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MDIO_PMA_REG_CTRL, &ctrl);
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if (!(ctrl & (1<<15)))
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break;
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msleep(1);
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@ -8807,6 +8899,329 @@ static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy,
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break;
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}
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}
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/******************************************************************/
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/* 54616S PHY SECTION */
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/******************************************************************/
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static int bnx2x_54616s_config_init(struct bnx2x_phy *phy,
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struct link_params *params,
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struct link_vars *vars)
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{
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struct bnx2x *bp = params->bp;
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u8 port;
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u16 autoneg_val, an_1000_val, an_10_100_val, fc_val, temp;
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u32 cfg_pin;
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DP(NETIF_MSG_LINK, "54616S cfg init\n");
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usleep_range(1000, 1000);
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/* This works with E3 only, no need to check the chip
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before determining the port. */
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port = params->port;
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cfg_pin = (REG_RD(bp, params->shmem_base +
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offsetof(struct shmem_region,
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dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
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PORT_HW_CFG_E3_PHY_RESET_MASK) >>
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PORT_HW_CFG_E3_PHY_RESET_SHIFT;
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/* Drive pin high to bring the GPHY out of reset. */
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bnx2x_set_cfg_pin(bp, cfg_pin, 1);
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/* wait for GPHY to reset */
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msleep(50);
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/* reset phy */
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bnx2x_cl22_write(bp, phy,
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MDIO_PMA_REG_CTRL, 0x8000);
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bnx2x_wait_reset_complete(bp, phy, params);
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/*wait for GPHY to reset */
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msleep(50);
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/* Configure LED4: set to INTR (0x6). */
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/* Accessing shadow register 0xe. */
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bnx2x_cl22_write(bp, phy,
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MDIO_REG_GPHY_SHADOW,
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MDIO_REG_GPHY_SHADOW_LED_SEL2);
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bnx2x_cl22_read(bp, phy,
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MDIO_REG_GPHY_SHADOW,
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&temp);
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temp &= ~(0xf << 4);
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temp |= (0x6 << 4);
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bnx2x_cl22_write(bp, phy,
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MDIO_REG_GPHY_SHADOW,
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MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
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/* Configure INTR based on link status change. */
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bnx2x_cl22_write(bp, phy,
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MDIO_REG_INTR_MASK,
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~MDIO_REG_INTR_MASK_LINK_STATUS);
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/* Flip the signal detect polarity (set 0x1c.0x1e[8]). */
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bnx2x_cl22_write(bp, phy,
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MDIO_REG_GPHY_SHADOW,
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MDIO_REG_GPHY_SHADOW_AUTO_DET_MED);
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bnx2x_cl22_read(bp, phy,
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MDIO_REG_GPHY_SHADOW,
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&temp);
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temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD;
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bnx2x_cl22_write(bp, phy,
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MDIO_REG_GPHY_SHADOW,
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MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
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/* Set up fc */
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/* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
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bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
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fc_val = 0;
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if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
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MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC)
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fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
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if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
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MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
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fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
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/* read all advertisement */
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bnx2x_cl22_read(bp, phy,
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0x09,
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&an_1000_val);
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bnx2x_cl22_read(bp, phy,
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0x04,
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&an_10_100_val);
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bnx2x_cl22_read(bp, phy,
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MDIO_PMA_REG_CTRL,
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&autoneg_val);
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/* Disable forced speed */
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autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
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an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8) | (1<<10) |
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(1<<11));
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if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
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(phy->speed_cap_mask &
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PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
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(phy->req_line_speed == SPEED_1000)) {
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an_1000_val |= (1<<8);
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autoneg_val |= (1<<9 | 1<<12);
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if (phy->req_duplex == DUPLEX_FULL)
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an_1000_val |= (1<<9);
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DP(NETIF_MSG_LINK, "Advertising 1G\n");
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} else
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an_1000_val &= ~((1<<8) | (1<<9));
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bnx2x_cl22_write(bp, phy,
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0x09,
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an_1000_val);
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bnx2x_cl22_read(bp, phy,
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0x09,
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&an_1000_val);
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/* set 100 speed advertisement */
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if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
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(phy->speed_cap_mask &
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(PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
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PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)))) {
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an_10_100_val |= (1<<7);
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/* Enable autoneg and restart autoneg for legacy speeds */
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autoneg_val |= (1<<9 | 1<<12);
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if (phy->req_duplex == DUPLEX_FULL)
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an_10_100_val |= (1<<8);
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DP(NETIF_MSG_LINK, "Advertising 100M\n");
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}
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/* set 10 speed advertisement */
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if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
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(phy->speed_cap_mask &
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(PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
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PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)))) {
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an_10_100_val |= (1<<5);
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autoneg_val |= (1<<9 | 1<<12);
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if (phy->req_duplex == DUPLEX_FULL)
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an_10_100_val |= (1<<6);
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DP(NETIF_MSG_LINK, "Advertising 10M\n");
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}
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/* Only 10/100 are allowed to work in FORCE mode */
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if (phy->req_line_speed == SPEED_100) {
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autoneg_val |= (1<<13);
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/* Enabled AUTO-MDIX when autoneg is disabled */
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bnx2x_cl22_write(bp, phy,
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0x18,
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(1<<15 | 1<<9 | 7<<0));
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DP(NETIF_MSG_LINK, "Setting 100M force\n");
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}
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if (phy->req_line_speed == SPEED_10) {
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/* Enabled AUTO-MDIX when autoneg is disabled */
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bnx2x_cl22_write(bp, phy,
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0x18,
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(1<<15 | 1<<9 | 7<<0));
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DP(NETIF_MSG_LINK, "Setting 10M force\n");
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}
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bnx2x_cl22_write(bp, phy,
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0x04,
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an_10_100_val | fc_val);
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if (phy->req_duplex == DUPLEX_FULL)
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autoneg_val |= (1<<8);
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bnx2x_cl22_write(bp, phy,
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MDIO_PMA_REG_CTRL, autoneg_val);
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return 0;
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}
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static void bnx2x_54616s_set_link_led(struct bnx2x_phy *phy,
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struct link_params *params, u8 mode)
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{
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struct bnx2x *bp = params->bp;
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DP(NETIF_MSG_LINK, "54616S set link led (mode=%x)\n", mode);
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switch (mode) {
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case LED_MODE_FRONT_PANEL_OFF:
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case LED_MODE_OFF:
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case LED_MODE_OPER:
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case LED_MODE_ON:
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default:
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break;
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}
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return;
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}
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static void bnx2x_54616s_link_reset(struct bnx2x_phy *phy,
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struct link_params *params)
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{
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struct bnx2x *bp = params->bp;
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u32 cfg_pin;
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u8 port;
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/* This works with E3 only, no need to check the chip
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before determining the port. */
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port = params->port;
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cfg_pin = (REG_RD(bp, params->shmem_base +
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offsetof(struct shmem_region,
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dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
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PORT_HW_CFG_E3_PHY_RESET_MASK) >>
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PORT_HW_CFG_E3_PHY_RESET_SHIFT;
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/* Drive pin low to put GPHY in reset. */
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bnx2x_set_cfg_pin(bp, cfg_pin, 0);
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}
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static u8 bnx2x_54616s_read_status(struct bnx2x_phy *phy,
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struct link_params *params,
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struct link_vars *vars)
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{
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struct bnx2x *bp = params->bp;
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u16 val;
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u8 link_up = 0;
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u16 legacy_status, legacy_speed;
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/* Get speed operation status */
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bnx2x_cl22_read(bp, phy,
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0x19,
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&legacy_status);
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DP(NETIF_MSG_LINK, "54616S read_status: 0x%x\n", legacy_status);
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/* Read status to clear the PHY interrupt. */
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bnx2x_cl22_read(bp, phy,
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MDIO_REG_INTR_STATUS,
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&val);
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link_up = ((legacy_status & (1<<2)) == (1<<2));
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if (link_up) {
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legacy_speed = (legacy_status & (7<<8));
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if (legacy_speed == (7<<8)) {
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vars->line_speed = SPEED_1000;
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vars->duplex = DUPLEX_FULL;
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} else if (legacy_speed == (6<<8)) {
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vars->line_speed = SPEED_1000;
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vars->duplex = DUPLEX_HALF;
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} else if (legacy_speed == (5<<8)) {
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vars->line_speed = SPEED_100;
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vars->duplex = DUPLEX_FULL;
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}
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/* Omitting 100Base-T4 for now */
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else if (legacy_speed == (3<<8)) {
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vars->line_speed = SPEED_100;
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vars->duplex = DUPLEX_HALF;
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} else if (legacy_speed == (2<<8)) {
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vars->line_speed = SPEED_10;
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vars->duplex = DUPLEX_FULL;
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} else if (legacy_speed == (1<<8)) {
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vars->line_speed = SPEED_10;
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vars->duplex = DUPLEX_HALF;
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} else /* Should not happen */
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vars->line_speed = 0;
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DP(NETIF_MSG_LINK, "Link is up in %dMbps,"
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" is_duplex_full= %d\n", vars->line_speed,
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(vars->duplex == DUPLEX_FULL));
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/* Check legacy speed AN resolution */
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bnx2x_cl22_read(bp, phy,
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0x01,
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&val);
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if (val & (1<<5))
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vars->link_status |=
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LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
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bnx2x_cl22_read(bp, phy,
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0x06,
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&val);
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if ((val & (1<<0)) == 0)
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vars->link_status |=
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LINK_STATUS_PARALLEL_DETECTION_USED;
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DP(NETIF_MSG_LINK, "BCM54616S: link speed is %d\n",
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vars->line_speed);
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bnx2x_ext_phy_resolve_fc(phy, params, vars);
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}
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return link_up;
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}
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||||
static void bnx2x_54616s_config_loopback(struct bnx2x_phy *phy,
|
||||
struct link_params *params)
|
||||
{
|
||||
struct bnx2x *bp = params->bp;
|
||||
u16 val;
|
||||
u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
|
||||
|
||||
DP(NETIF_MSG_LINK, "2PMA/PMD ext_phy_loopback: 54616s\n");
|
||||
|
||||
/* Enable master/slave manual mmode and set to master */
|
||||
/* mii write 9 [bits set 11 12] */
|
||||
bnx2x_cl22_write(bp, phy, 0x09, 3<<11);
|
||||
|
||||
/* forced 1G and disable autoneg */
|
||||
/* set val [mii read 0] */
|
||||
/* set val [expr $val & [bits clear 6 12 13]] */
|
||||
/* set val [expr $val | [bits set 6 8]] */
|
||||
/* mii write 0 $val */
|
||||
bnx2x_cl22_read(bp, phy, 0x00, &val);
|
||||
val &= ~((1<<6) | (1<<12) | (1<<13));
|
||||
val |= (1<<6) | (1<<8);
|
||||
bnx2x_cl22_write(bp, phy, 0x00, val);
|
||||
|
||||
/* Set external loopback and Tx using 6dB coding */
|
||||
/* mii write 0x18 7 */
|
||||
/* set val [mii read 0x18] */
|
||||
/* mii write 0x18 [expr $val | [bits set 10 15]] */
|
||||
bnx2x_cl22_write(bp, phy, 0x18, 7);
|
||||
bnx2x_cl22_read(bp, phy, 0x18, &val);
|
||||
bnx2x_cl22_write(bp, phy, 0x18, val | (1<<10) | (1<<15));
|
||||
|
||||
/* This register opens the gate for the UMAC despite its name */
|
||||
REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
|
||||
|
||||
/*
|
||||
* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
|
||||
* length used by the MAC receive logic to check frames.
|
||||
*/
|
||||
REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
|
||||
}
|
||||
|
||||
/******************************************************************/
|
||||
/* SFX7101 PHY SECTION */
|
||||
/******************************************************************/
|
||||
@ -9390,6 +9805,39 @@ static struct bnx2x_phy phy_84833 = {
|
||||
.phy_specific_func = (phy_specific_func_t)NULL
|
||||
};
|
||||
|
||||
static struct bnx2x_phy phy_54616s = {
|
||||
.type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616,
|
||||
.addr = 0xff,
|
||||
.def_md_devad = 0,
|
||||
.flags = FLAGS_INIT_XGXS_FIRST,
|
||||
.rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
|
||||
.tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
|
||||
.mdio_ctrl = 0,
|
||||
.supported = (SUPPORTED_10baseT_Half |
|
||||
SUPPORTED_10baseT_Full |
|
||||
SUPPORTED_100baseT_Half |
|
||||
SUPPORTED_100baseT_Full |
|
||||
SUPPORTED_1000baseT_Full |
|
||||
SUPPORTED_TP |
|
||||
SUPPORTED_Autoneg |
|
||||
SUPPORTED_Pause |
|
||||
SUPPORTED_Asym_Pause),
|
||||
.media_type = ETH_PHY_BASE_T,
|
||||
.ver_addr = 0,
|
||||
.req_flow_ctrl = 0,
|
||||
.req_line_speed = 0,
|
||||
.speed_cap_mask = 0,
|
||||
/* req_duplex = */0,
|
||||
/* rsrv = */0,
|
||||
.config_init = (config_init_t)bnx2x_54616s_config_init,
|
||||
.read_status = (read_status_t)bnx2x_54616s_read_status,
|
||||
.link_reset = (link_reset_t)bnx2x_54616s_link_reset,
|
||||
.config_loopback = (config_loopback_t)bnx2x_54616s_config_loopback,
|
||||
.format_fw_ver = (format_fw_ver_t)NULL,
|
||||
.hw_reset = (hw_reset_t)NULL,
|
||||
.set_link_led = (set_link_led_t)bnx2x_54616s_set_link_led,
|
||||
.phy_specific_func = (phy_specific_func_t)NULL
|
||||
};
|
||||
/*****************************************************************/
|
||||
/* */
|
||||
/* Populate the phy according. Main function: bnx2x_populate_phy */
|
||||
@ -9630,6 +10078,9 @@ static int bnx2x_populate_ext_phy(struct bnx2x *bp,
|
||||
case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
|
||||
*phy = phy_84833;
|
||||
break;
|
||||
case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616:
|
||||
*phy = phy_54616s;
|
||||
break;
|
||||
case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
|
||||
*phy = phy_7101;
|
||||
break;
|
||||
|
||||
@ -5420,7 +5420,9 @@
|
||||
#define EMAC_LED_OVERRIDE (1L<<0)
|
||||
#define EMAC_LED_TRAFFIC (1L<<6)
|
||||
#define EMAC_MDIO_COMM_COMMAND_ADDRESS (0L<<26)
|
||||
#define EMAC_MDIO_COMM_COMMAND_READ_22 (2L<<26)
|
||||
#define EMAC_MDIO_COMM_COMMAND_READ_45 (3L<<26)
|
||||
#define EMAC_MDIO_COMM_COMMAND_WRITE_22 (1L<<26)
|
||||
#define EMAC_MDIO_COMM_COMMAND_WRITE_45 (1L<<26)
|
||||
#define EMAC_MDIO_COMM_DATA (0xffffL<<0)
|
||||
#define EMAC_MDIO_COMM_START_BUSY (1L<<29)
|
||||
@ -6737,6 +6739,16 @@ Theotherbitsarereservedandshouldbezero*/
|
||||
|
||||
#define DIGITAL5_ACTUAL_SPEED_TX_MASK 0x003f
|
||||
|
||||
/* 54616s */
|
||||
#define MDIO_REG_INTR_STATUS 0x1a
|
||||
#define MDIO_REG_INTR_MASK 0x1b
|
||||
#define MDIO_REG_INTR_MASK_LINK_STATUS (0x1 << 1)
|
||||
#define MDIO_REG_GPHY_SHADOW 0x1c
|
||||
#define MDIO_REG_GPHY_SHADOW_LED_SEL2 (0x0e << 10)
|
||||
#define MDIO_REG_GPHY_SHADOW_WR_ENA (0x1 << 15)
|
||||
#define MDIO_REG_GPHY_SHADOW_AUTO_DET_MED (0x1e << 10)
|
||||
#define MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD (0x1 << 8)
|
||||
|
||||
#define IGU_FUNC_BASE 0x0400
|
||||
|
||||
#define IGU_ADDR_MSIX 0x0000
|
||||
|
||||
Loading…
Reference in New Issue
Block a user