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MIPS: kernel: cpu-probe: Detect unique RI/XI exceptions

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Detect if the core supports unique exception codes for the
Read-Inhibit and Execute-Inhibit exceptions and set the
option accordingly. The RI/XI exception support is detected
by setting the 27th bit (IEC) of the PageGrain C0 register
and reading back the value of that register to verify the
bit is enabled.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/7340/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Leonid Yegoshin 2014-07-15 14:09:57 +01:00 committed by Ralf Baechle
parent 5890f70f15
commit 6575b1d417
2 changed files with 10 additions and 0 deletions
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1
arch/mips/include/asm/mipsregs.h
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@ -265,6 +265,7 @@
#define PG_XIE (_ULCAST_(1) << 30) #define PG_XIE (_ULCAST_(1) << 30)
#define PG_ELPA (_ULCAST_(1) << 29) #define PG_ELPA (_ULCAST_(1) << 29)
#define PG_ESP (_ULCAST_(1) << 28) #define PG_ESP (_ULCAST_(1) << 28)
#define PG_IEC (_ULCAST_(1) << 27)
/* /*
* R4x00 interrupt enable / cause bits * R4x00 interrupt enable / cause bits

9
arch/mips/kernel/cpu-probe.c
View File

@ -438,6 +438,15 @@ static void decode_configs(struct cpuinfo_mips *c)
mips_probe_watch_registers(c); mips_probe_watch_registers(c);
if (cpu_has_rixi) {
/* Enable the RIXI exceptions */
write_c0_pagegrain(read_c0_pagegrain() | PG_IEC);
back_to_back_c0_hazard();
/* Verify the IEC bit is set */
if (read_c0_pagegrain() & PG_IEC)
c->options |= MIPS_CPU_RIXIEX;
}
#ifndef CONFIG_MIPS_CPS #ifndef CONFIG_MIPS_CPS
if (cpu_has_mips_r2) { if (cpu_has_mips_r2) {
c->core = get_ebase_cpunum(); c->core = get_ebase_cpunum();