forked from Minki/linux
wil6210: support for "sparrow" hardware
New hardware release appears; it require some changes to properly support it. Introduce struct wil_board and "board" attribute in wil6210_priv; keep hardware variant information in this structure. fill it on probe(). Used in the reset flow. Signed-off-by: Vladimir Kondratiev <qca_vkondrat@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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5235cd2121
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6508281b0b
@ -314,8 +314,9 @@ static void wil_target_reset(struct wil6210_priv *wil)
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int delay = 0;
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int delay = 0;
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u32 hw_state;
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u32 hw_state;
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u32 rev_id;
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u32 rev_id;
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bool is_sparrow = (wil->board->board == WIL_BOARD_SPARROW);
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wil_dbg_misc(wil, "Resetting...\n");
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wil_dbg_misc(wil, "Resetting \"%s\"...\n", wil->board->name);
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/* register read */
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/* register read */
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#define R(a) ioread32(wil->csr + HOSTADDR(a))
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#define R(a) ioread32(wil->csr + HOSTADDR(a))
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@ -328,35 +329,59 @@ static void wil_target_reset(struct wil6210_priv *wil)
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wil->hw_version = R(RGF_USER_FW_REV_ID);
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wil->hw_version = R(RGF_USER_FW_REV_ID);
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rev_id = wil->hw_version & 0xff;
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rev_id = wil->hw_version & 0xff;
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/* Clear MAC link up */
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S(RGF_HP_CTRL, BIT(15));
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/* hpal_perst_from_pad_src_n_mask */
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/* hpal_perst_from_pad_src_n_mask */
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S(RGF_USER_CLKS_CTL_SW_RST_MASK_0, BIT(6));
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S(RGF_USER_CLKS_CTL_SW_RST_MASK_0, BIT(6));
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/* car_perst_rst_src_n_mask */
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/* car_perst_rst_src_n_mask */
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S(RGF_USER_CLKS_CTL_SW_RST_MASK_0, BIT(7));
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S(RGF_USER_CLKS_CTL_SW_RST_MASK_0, BIT(7));
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wmb(); /* order is important here */
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wmb(); /* order is important here */
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if (is_sparrow) {
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W(RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_0, 0x3ff81f);
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wmb(); /* order is important here */
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}
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W(RGF_USER_MAC_CPU_0, BIT(1)); /* mac_cpu_man_rst */
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W(RGF_USER_MAC_CPU_0, BIT(1)); /* mac_cpu_man_rst */
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W(RGF_USER_USER_CPU_0, BIT(1)); /* user_cpu_man_rst */
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W(RGF_USER_USER_CPU_0, BIT(1)); /* user_cpu_man_rst */
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wmb(); /* order is important here */
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wmb(); /* order is important here */
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W(RGF_USER_CLKS_CTL_SW_RST_VEC_2, 0xFE000000);
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W(RGF_USER_CLKS_CTL_SW_RST_VEC_2, 0xFE000000);
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W(RGF_USER_CLKS_CTL_SW_RST_VEC_1, 0x0000003F);
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W(RGF_USER_CLKS_CTL_SW_RST_VEC_1, 0x0000003F);
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W(RGF_USER_CLKS_CTL_SW_RST_VEC_3, 0x00000170);
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W(RGF_USER_CLKS_CTL_SW_RST_VEC_3, is_sparrow ? 0x000000B0 : 0x00000170);
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W(RGF_USER_CLKS_CTL_SW_RST_VEC_0, 0xFFE7FC00);
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W(RGF_USER_CLKS_CTL_SW_RST_VEC_0, 0xFFE7FC00);
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wmb(); /* order is important here */
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wmb(); /* order is important here */
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if (is_sparrow) {
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W(RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_0, 0x0);
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wmb(); /* order is important here */
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}
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W(RGF_USER_CLKS_CTL_SW_RST_VEC_3, 0);
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W(RGF_USER_CLKS_CTL_SW_RST_VEC_3, 0);
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W(RGF_USER_CLKS_CTL_SW_RST_VEC_2, 0);
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W(RGF_USER_CLKS_CTL_SW_RST_VEC_2, 0);
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W(RGF_USER_CLKS_CTL_SW_RST_VEC_1, 0);
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W(RGF_USER_CLKS_CTL_SW_RST_VEC_1, 0);
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W(RGF_USER_CLKS_CTL_SW_RST_VEC_0, 0);
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W(RGF_USER_CLKS_CTL_SW_RST_VEC_0, 0);
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wmb(); /* order is important here */
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wmb(); /* order is important here */
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W(RGF_USER_CLKS_CTL_SW_RST_VEC_3, 0x00000001);
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if (is_sparrow) {
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if (rev_id == 1) {
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W(RGF_USER_CLKS_CTL_SW_RST_VEC_3, 0x00000003);
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W(RGF_USER_CLKS_CTL_SW_RST_VEC_2, 0x00000080);
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/* reset A2 PCIE AHB */
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} else {
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W(RGF_PCIE_LOS_COUNTER_CTL, BIT(6) | BIT(8));
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W(RGF_USER_CLKS_CTL_SW_RST_VEC_2, 0x00008000);
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W(RGF_USER_CLKS_CTL_SW_RST_VEC_2, 0x00008000);
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} else {
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W(RGF_USER_CLKS_CTL_SW_RST_VEC_3, 0x00000001);
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if (rev_id == 1) {
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/* reset A1 BOTH PCIE AHB & PCIE RGF */
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W(RGF_USER_CLKS_CTL_SW_RST_VEC_2, 0x00000080);
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} else {
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W(RGF_PCIE_LOS_COUNTER_CTL, BIT(6) | BIT(8));
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W(RGF_USER_CLKS_CTL_SW_RST_VEC_2, 0x00008000);
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}
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}
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}
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/* TODO: check order here!!! Erez code is different */
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W(RGF_USER_CLKS_CTL_SW_RST_VEC_0, 0);
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W(RGF_USER_CLKS_CTL_SW_RST_VEC_0, 0);
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wmb(); /* order is important here */
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wmb(); /* order is important here */
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@ -371,7 +396,8 @@ static void wil_target_reset(struct wil6210_priv *wil)
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}
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}
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} while (hw_state != HW_MACHINE_BOOT_DONE);
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} while (hw_state != HW_MACHINE_BOOT_DONE);
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if (rev_id == 2)
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/* TODO: Erez check rev_id != 1 */
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if (!is_sparrow && (rev_id != 1))
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W(RGF_PCIE_LOS_COUNTER_CTL, BIT(8));
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W(RGF_PCIE_LOS_COUNTER_CTL, BIT(8));
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C(RGF_USER_CLKS_CTL_0, BIT_USER_CLKS_RST_PWGD);
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C(RGF_USER_CLKS_CTL_0, BIT_USER_CLKS_RST_PWGD);
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@ -122,10 +122,12 @@ static int wil_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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struct wil6210_priv *wil;
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struct wil6210_priv *wil;
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struct device *dev = &pdev->dev;
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struct device *dev = &pdev->dev;
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void __iomem *csr;
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void __iomem *csr;
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struct wil_board *board = (struct wil_board *)id->driver_data;
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int rc;
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int rc;
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/* check HW */
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/* check HW */
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dev_info(&pdev->dev, WIL_NAME " device found [%04x:%04x] (rev %x)\n",
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dev_info(&pdev->dev, WIL_NAME
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" \"%s\" device found [%04x:%04x] (rev %x)\n", board->name,
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(int)pdev->vendor, (int)pdev->device, (int)pdev->revision);
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(int)pdev->vendor, (int)pdev->device, (int)pdev->revision);
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if (pci_resource_len(pdev, 0) != WIL6210_MEM_SIZE) {
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if (pci_resource_len(pdev, 0) != WIL6210_MEM_SIZE) {
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@ -175,6 +177,7 @@ static int wil_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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pci_set_drvdata(pdev, wil);
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pci_set_drvdata(pdev, wil);
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wil->pdev = pdev;
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wil->pdev = pdev;
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wil->board = board;
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wil6210_clear_irq(wil);
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wil6210_clear_irq(wil);
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/* FW should raise IRQ when ready */
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/* FW should raise IRQ when ready */
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@ -225,8 +228,21 @@ static void wil_pcie_remove(struct pci_dev *pdev)
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pci_disable_device(pdev);
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pci_disable_device(pdev);
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}
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}
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static DEFINE_PCI_DEVICE_TABLE(wil6210_pcie_ids) = {
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static const struct wil_board wil_board_marlon = {
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{ PCI_DEVICE(0x1ae9, 0x0301) },
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.board = WIL_BOARD_MARLON,
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.name = "marlon",
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};
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static const struct wil_board wil_board_sparrow = {
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.board = WIL_BOARD_SPARROW,
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.name = "sparrow",
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};
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static const struct pci_device_id wil6210_pcie_ids[] = {
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{ PCI_DEVICE(0x1ae9, 0x0301),
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.driver_data = (kernel_ulong_t)&wil_board_marlon },
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{ PCI_DEVICE(0x1ae9, 0x0310),
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.driver_data = (kernel_ulong_t)&wil_board_sparrow },
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{ /* end: all zeroes */ },
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{ /* end: all zeroes */ },
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};
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};
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MODULE_DEVICE_TABLE(pci, wil6210_pcie_ids);
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MODULE_DEVICE_TABLE(pci, wil6210_pcie_ids);
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@ -24,6 +24,13 @@
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#define WIL_NAME "wil6210"
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#define WIL_NAME "wil6210"
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struct wil_board {
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int board;
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#define WIL_BOARD_MARLON (1)
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#define WIL_BOARD_SPARROW (2)
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const char * const name;
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};
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/**
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/**
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* extract bits [@b0:@b1] (inclusive) from the value @x
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* extract bits [@b0:@b1] (inclusive) from the value @x
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* it should be @b0 <= @b1, or result is incorrect
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* it should be @b0 <= @b1, or result is incorrect
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@ -93,6 +100,7 @@ struct RGF_ICR {
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#define RGF_USER_CLKS_CTL_SW_RST_MASK_0 (0x880b14)
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#define RGF_USER_CLKS_CTL_SW_RST_MASK_0 (0x880b14)
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#define RGF_USER_USER_ICR (0x880b4c) /* struct RGF_ICR */
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#define RGF_USER_USER_ICR (0x880b4c) /* struct RGF_ICR */
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#define BIT_USER_USER_ICR_SW_INT_2 BIT(18)
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#define BIT_USER_USER_ICR_SW_INT_2 BIT(18)
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#define RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_0 (0x880c18)
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#define RGF_DMA_EP_TX_ICR (0x881bb4) /* struct RGF_ICR */
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#define RGF_DMA_EP_TX_ICR (0x881bb4) /* struct RGF_ICR */
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#define BIT_DMA_EP_TX_ICR_TX_DONE BIT(0)
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#define BIT_DMA_EP_TX_ICR_TX_DONE BIT(0)
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@ -121,6 +129,7 @@ struct RGF_ICR {
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#define BIT_DMA_PSEUDO_CAUSE_TX BIT(1)
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#define BIT_DMA_PSEUDO_CAUSE_TX BIT(1)
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#define BIT_DMA_PSEUDO_CAUSE_MISC BIT(2)
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#define BIT_DMA_PSEUDO_CAUSE_MISC BIT(2)
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#define RGF_HP_CTRL (0x88265c)
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#define RGF_PCIE_LOS_COUNTER_CTL (0x882dc4)
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#define RGF_PCIE_LOS_COUNTER_CTL (0x882dc4)
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/* popular locations */
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/* popular locations */
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@ -365,6 +374,7 @@ struct wil6210_priv {
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ulong status;
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ulong status;
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u32 fw_version;
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u32 fw_version;
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u32 hw_version;
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u32 hw_version;
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struct wil_board *board;
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u8 n_mids; /* number of additional MIDs as reported by FW */
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u8 n_mids; /* number of additional MIDs as reported by FW */
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int recovery_count; /* num of FW recovery attempts in a short time */
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int recovery_count; /* num of FW recovery attempts in a short time */
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unsigned long last_fw_recovery; /* jiffies of last fw recovery */
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unsigned long last_fw_recovery; /* jiffies of last fw recovery */
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